Display panel including lower pattern on first barrier layer and display device including the same

Patent metadata

Field	Value
Publication number	US-12219830-B2
Application number	US-202117361072-A
Country	US
Kind code	B2
Filing date	Jun 28, 2021
Priority date	Oct 5, 2020
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

A display device includes a substrate, a first barrier layer on the substrate, a lower pattern on the first barrier layer and having a mesh shape defining a disconnection area, a second barrier layer on the first barrier layer, covering the lower pattern, and contacting the first barrier layer in the disconnection area, and a first active pattern on the second barrier layer and overlapping the lower pattern, a gate electrode on the first active pattern and overlapping the lower pattern, a first gate line on the first active pattern extending in a first direction, a second active pattern on the first gate line, a second gate line on the second active pattern extending in the first direction, and a data line on the second gate line extending in a second direction crossing the first direction.

First claim

What is claimed is:

1. A display panel comprising:
a substrate;
a first barrier layer on the substrate;
a lower pattern on the first barrier layer and having a mesh shape defining a disconnection area;
a second barrier layer on the first barrier layer, covering the lower pattern, and contacting the first barrier layer in the disconnection area;
a first active pattern on the second barrier layer and overlapping the lower pattern;
at least one gate electrode on the first active pattern and overlapping the lower pattern;
at least one first gate line on the first active pattern, extending in a first direction, and adjacent to a first side of the at least one gate electrode in a plan view;
a second active pattern on the first gate line;
at least one second gate line on the second active pattern, extending in the first direction, and adjacent to a second side of the at least one gate electrode in the plan view, wherein the second side is opposite the first side; and
at least one data line on the second gate line and extending in a second direction crossing the first direction.

2. The display panel of claim 1 , wherein the lower pattern comprises:
a first pattern extending in the second direction; and
a second pattern extending in the second direction and spaced apart from the first pattern along the first direction,
wherein the disconnection area is between the first pattern and the second pattern, and
wherein the first pattern and the second pattern are not connected to each other.

3. The display panel of claim 2 , wherein the first pattern and the second pattern have the same shape.

4. The display panel of claim 2 , wherein the at least one gate electrode comprises first to fourth gate electrodes arranged with each other along the first direction, and
wherein the first pattern comprises:
a first auxiliary pattern overlapping the first gate electrode;
a second auxiliary pattern overlapping the second gate electrode;
a third auxiliary pattern overlapping the third gate electrode; and
a fourth auxiliary pattern overlapping the fourth gate electrode.

5. The display panel of claim 4 , wherein the second auxiliary pattern is symmetrical in shape with the first auxiliary pattern in the first direction, and
the fourth auxiliary pattern is symmetrical in shape with the third auxiliary pattern in the first direction.

6. The display panel of claim 4 , wherein the first to fourth auxiliary patterns are connected to each other.

7. The display panel of claim 4 , further comprising:
at least one power voltage line in a same layer as the data line, extending in the second direction, and being to transmit a power voltage,
wherein the first auxiliary pattern overlaps the power voltage line.

8. The display panel of claim 2 , wherein the second pattern is symmetrical in shape with the first pattern in the first direction.

9. The display panel of claim 8 , wherein the at least one gate electrode comprises a first gate electrode and a second gate electrode which are arranged with each other along the first direction,
the first pattern overlaps the first gate electrode, and
the second pattern overlaps the second gate electrode.

10. The display panel of claim 8 , further comprising:
at least one power voltage line in a same layer as the data line, extending in the second direction, and being to transmit a power voltage,
wherein the first pattern overlaps the power voltage line.

11. The display panel of claim 1 , wherein the lower pattern comprises:
a first pattern extending in the first direction; and
a second pattern extending in the first direction and spaced from the first pattern in the second direction, and
wherein the disconnection area is between the first pattern and the second pattern, and
the first pattern and the second pattern are not connected to each other.

12. The display panel of claim 11 , wherein the first pattern and the second pattern are the same in shape.

13. The display panel of claim 11 , wherein the at least one gate electrode comprises first and second gate electrodes arranged with each other along the second direction,
the first pattern overlaps the first gate electrode, and
the second pattern overlaps the second gate electrode.

14. The display panel of claim 1 , the second barrier layer is greater in thickness than the first barrier layer.

15. The display panel of claim 1 , wherein the lower pattern comprises a same metal as the at least one gate electrode.

16. The display panel of claim 1 , wherein the first active pattern comprises a silicon semiconductor, and
the second active pattern comprises an oxide semiconductor.

17. A display device comprising a display panel,
wherein the display panel comprises:
a substrate;
a first barrier layer on the substrate;
a lower pattern on the first barrier layer and having a mesh shape defining a disconnection area;
a second barrier layer on the first barrier layer, covering the lower pattern, and contacting the first barrier layer in the disconnection area;
a first active pattern on the second barrier layer and overlapping the lower pattern;
at least one gate electrode on the first active pattern and overlapping the lower pattern;
at least one first gate line on the first active pattern, extending in a first direction, and adjacent to a first side of the at least one gate electrode on a plane;
a second active pattern on the first gate line;
at least one second gate line on the second active pattern, extending in the first direction, and adjacent to a second side of the at least one gate electrode on a plane, wherein the second side is opposite the first side; and
at least one data line on the second gate line and extending in a second direction crossing the first direction.

18. The display device of claim 17 , further comprising:
an optical sensor module under the display panel and overlapping a fingerprint recognition area; and
an air layer between the display panel and the optical sensor module and overlapping the fingerprint recognition area,
wherein the lower pattern overlaps the fingerprint recognition area.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Na-Young
• Kim Dong-Hwi
• Kim Cheolsu
• Bae Injun
• Seo Woori
• Oh Youngtaek

Classifications

• H10K59/8731

  multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers · CPC title

• H10K59/65

  OLEDs integrated with inorganic image sensors · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title