Non-volatile memory device, storage device including the same, and operating method thereof

Patent metadata

Field	Value
Publication number	US-12217802-B2
Application number	US-202217648311-A
Country	US
Kind code	B2
Filing date	Jan 19, 2022
Priority date	Jun 28, 2021
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

A non-volatile memory device includes a meta area having a first region storing first initial data, and second regions storing second initial data, different from each other; a user area configured to store user data; an initialization register configured to store the first initial data or update the second initial data in whole or in part; and control logic configured to perform a read operation, a program operation, or an erase operation using the initial data stored in the initialization register.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a meta area having a first region storing first initial data, and second regions storing second initial data, different from each other;
a user area configured to store user data;
an initialization register configured to store the first initial data or the second initial data, and to update the second initial data in whole or in part; and
control logic configured to receive a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, and a data strobe signal through control pins and latch a command or an address at an edge of the write enable signal according to the chip enable signal and the address latch enable signal, to perform a read operation, a program operation, or an erase operation using the initial data stored in the initialization register,
wherein one of the first initial data or the second initial data comprises at least one performance parameter related to an operation time of the non-volatile memory device,
wherein the other of the first initial data or the second initial data comprises at least one reliability parameter related to at least one of retention, endurance, voltage or verification of the non-volatile memory device,
wherein one of the first initial data or the second initial data is provided in common, and the other of the first initial data or the second initial data is selectable by a user.

2. The non-volatile memory device of claim 1 ,
wherein, during a power-up operation, an initial data read command is received externally,
wherein the at least one performance parameter includes a plurality of times for a respective plurality of memory operations of the non-volatile memory device,
wherein the at least one reliability parameter includes a plurality of voltages for the respective plurality of memory operations of the non-volatile memory device.

3. The non-volatile memory device of claim 2 , wherein the control logic is configured to read the first initial data stored in the first region in response to the initial data read command, and store the read first initial data in the initialization register.

4. The non-volatile memory device of claim 3 , wherein the control logic is configured to read the second initial data in a second region selected from among the second regions in response to the initial data read command, and store the read second initial data in a portion of the initialization register.

5. The non-volatile memory device of claim 3 , wherein the control logic is configured to read the second initial data stored in the second regions in response to the initial data read command, and store one among the different read second initial data in the initialization register.

6. The non-volatile memory device of claim 2 , wherein the initial data read command comprises a first initial data read command and a second initial data read command.

7. The non-volatile memory device of claim 6 , wherein the control logic is configured to read the first initial data stored in the first region in response to the first initial data read command, and read a second initial data stored in one among the second regions, in response to the second initial data read command.

8. The non-volatile memory device of claim 1 ,
wherein the meta area comprises a plurality of meta blocks having a plurality of memory cells connected to a plurality of word-lines and a plurality of bit-lines,
wherein meta block one of the plurality of meta blocks comprises the first region and the second region.

9. The non-volatile memory device of claim 1 ,
wherein the meta area comprises a plurality of meta blocks having a plurality of memory cells connected to a plurality of word-lines and a plurality of bit-lines,
wherein at least two meta blocks of the plurality of meta blocks comprise the first region and the second region.

10. The non-volatile memory device of claim 1 ,
wherein the first initial data comprises at least one performance parameter related to the read operation, the program operation, or the erase operation, and
wherein the second initial data comprises at least one reliability parameter related to the read operation, the program operation, or the erase operation.

11. An operating method in a storage device having a non-volatile memory device and a controller controlling the non-volatile memory device, comprising:
performing a power-up operation by supplying power;
selecting an application usage after the power-up operation;
reading initial data according to the application usage; and
setting a register of the non-volatile memory device with the read initial data,
wherein the reading initial data according to the application usage comprises:
reading first initial data related to a core operation from the non-volatile memory device; and
reading and updating second initial data, corresponding to the core operation, according to the application usage from the non-volatile memory device,
wherein one of the first initial data or the second initial data comprises at least one performance parameter related to an operation time of at least one memory operation,
wherein the other of the first initial data or the second initial data comprises at least one reliability parameter related to at least one of retention, endurance, voltage or verification of the at least one memory operation,
wherein one of the first initial data or the second initial data is provided in common, and the other of the first initial data or the second initial data is selectable by a user.

12. The method of claim 11 , further comprising transmitting an initialization operation request to the non-volatile memory device,
wherein the at least one performance parameter includes a plurality of times for a respective plurality of memory operations,
wherein the at least one reliability parameter includes a plurality of voltages for the respective plurality of memory operations.

13. The method of claim 12 ,
wherein the initialization operation request comprises an initial data read command, a first address, and a second address,
wherein the first address is an address indicating a region storing the first initial data, and
wherein the second address is an address indicating a region storing the second initial data.

14. The method of claim 11 , wherein the first initial data comprises a read time, a program time, or an erase time, for setting a memory operation.

15. The method of claim 11 , further comprising performing a read operation, a program operation, or an erase operation using data set in the register of the non-volatile memory device.

16. A non-volatile memory device comprising:
a memory cell array having a plurality of memory blocks having a plurality of memory cells connected to a plurality of word-lines and a plurality of bit-lines;
a row decoder configured to select a memory block, among the plurality of memory blocks, in response to an address;
a voltage generator configured to apply word-line voltages corresponding to a selected word-line and unselected word-lines, among the plurality of word-lines;
page buffers connected to the plurality of bit-lines and reading data from memory cells connected to the selected word-line of the selected memory block among the plurality of memory blocks; and
control logic configured to control the row decoder, the voltage generator, and the page buffers,
wherein at least one memory block, among the plurality of memory blocks, comprises a first region configured to store first initial data, and second regions c

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jooyong
• Park Sangwon
• Shin Dongjin
• Jeon Suchang
• Choi Seungyong

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/20 Primary

  Initialising; Data preset; Chip identification · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title