Method of improving programming operations in 3D NAND systems

Patent metadata

Field	Value
Publication number	US-12216907-B2
Application number	US-202218082265-A
Country	US
Kind code	B2
Filing date	Dec 15, 2022
Priority date	Nov 23, 2022
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

The present disclosure provides a method for performing a programming operation on a memory cell connected to a bit line and controlled by a word line. The method includes applying a first programming voltage signal to the word line to program the memory cell into a first state, applying a first voltage to the bit line, performing a verify operation when the memory cell is in a second state, determining a classification of the memory cell based on the verify operation, applying a second voltage to the bit line based on the determined classification, applying a second programming voltage signal to the word line to program the memory cell into the first state, applying a third voltage to the bit line, applying a third programming voltage signal to the word line to program the memory cell into the first state, and applying a fourth voltage to the bit line.

First claim

What is claimed is:

1. A method for programming a memory device, the method comprising:
performing a programming operation on a memory cell, wherein the memory cell is connected to a bit line and is controlled by a word line, wherein performing the programming operation comprises:
applying a first programming voltage signal to the word line to program the memory cell into a first programmed state;
applying a first voltage to the bit line;
subsequent to the applying the first voltage, performing a verify operation when the memory cell is in a second programmed state different from the first programmed state, wherein a second verify voltage of the second programmed state is lower than a first verify voltage of the first programmed state;
determining a classification of the memory cell based on the verify operation;
applying a second voltage to the bit line based on the determined classification;
applying a second programming voltage signal to the word line to program the memory cell into the first programmed state;
applying a third voltage to the bit line;
applying a third programming voltage signal to the word line to program the memory cell into the first programmed state; and
applying a fourth voltage to the bit line.

2. The method of claim 1 , wherein the applying the first voltage comprises applying a voltage larger than zero.

3. The method of claim 1 , wherein a target voltage of the second programmed state is lower than a target voltage of the first programmed state.

4. The method of claim 1 , wherein performing the verify operation comprises comparing a threshold voltage of the memory cell with a read reference voltage, wherein the read reference voltage is the second verify voltage of the second programmed state.

5. The method of claim 4 , wherein the determining the classification of the memory cell based on the verify operation comprises:
determining a classification of the memory cell as a first classification when the threshold voltage is larger than the read reference voltage, or
determining a classification of the memory cell as a second classification when the threshold voltage is smaller than the read reference voltage.

6. The method of claim 5 , wherein the applying the second voltage is applied so as to be equal to the first voltage based on the determined first classification of the memory cell, or as a zero voltage based on the determined second classification of the memory cell.

7. The method of claim 1 , wherein the third voltage is larger than the second voltage.

8. A three-dimensional (3D) NAND memory device, comprising:
a NAND string including a cell to be inhibited to program;
a word line driver;
a bit line driver; and
a controller configured to control the word line driver and the bit line driver to:
apply a first programming voltage signal to a word line to program a memory cell into a first programmed state;
apply a first voltage to a bit line;
subsequent to the applying the first voltage, perform a verify operation when the memory cell is in a second programmed state different from the first programmed state, wherein a second verify voltage of the second programmed state is lower than a first verify voltage of the first programmed state;
determine a classification of the memory cell based on the verify operation;
apply a second voltage to the bit line based on the determined classification;
apply a second programming voltage signal to the word line to program the memory cell into the first programmed state;
apply a third voltage to the bit line;
apply a third programming voltage signal to the word line to program the memory cell into the first programmed state; and
apply a fourth voltage to the bit line.

9. The 3D NAND memory device of claim 8 , wherein the applying the first voltage comprises applying a voltage larger than zero.

10. The 3D NAND memory device of claim 8 , wherein a target voltage of the second programmed state is lower than a target voltage of the first programmed state.

11. The 3D NAND memory device of claim 8 , wherein performing the verify operation comprises comparing a threshold voltage of the memory cell with a read reference voltage, wherein the read reference voltage is the second verify voltage of the second programmed state.

12. The 3D NAND memory device of claim 11 , wherein the determining the classification of the memory cell based on the verify operation comprises:
determining a classification of the memory cell as a first classification when the threshold voltage is larger than the read reference voltage, or
determining a classification of the memory cell as a second classification when the threshold voltage is smaller than the read reference voltage.

13. The 3D NAND memory device of claim 12 , wherein the applying the second voltage is applied so as to be equal to the first voltage based on the determined first classification of the memory cell, or as a zero voltage based on the determined second classification of the memory cell.

14. The 3D NAND memory device of claim 8 , wherein the third voltage is larger than the second voltage.

15. A non-transitory medium having instructions stored thereon that, upon execution by at least one controller, cause the at least one controller to perform a method of performing a programming operation of a memory device, the method comprising:
applying a first programming voltage signal to a word line to program a memory cell into a first programmed state;
applying a first voltage to a bit line;
subsequent to the applying the first voltage, performing a verify operation when the memory cell is in a second programmed state different from the first programmed state, wherein a second verify voltage of the second programmed state is lower than a first verify voltage of the first programmed state;
determining a classification of the memory cell based on the verify operation;
applying a second voltage to the bit line based on the determined classification;
applying a second programming voltage signal to the word line to program the memory cell into the first programmed state;
applying a third voltage to the bit line;
applying a third programming voltage signal to the word line to program the memory cell into the first programmed state; and
applying a fourth voltage to the bit line.

16. The non-transitory medium of claim 15 , wherein the applying the first voltage comprises applying a voltage larger than zero.

17. The non-transitory medium of claim 15 , wherein a target voltage of the second programmed state is lower than a target voltage of the first programmed state.

18. The non-transitory medium of claim 15 , wherein performing the verify operation comprises comparing a threshold voltage of the memory cell with a read reference voltage, wherein the read reference voltage is the second verify voltage of the second programmed state.

19. The non-transitory medium of claim 18 , wherein the determining the classification of the memory cell based on the verify operation comprises:
determining a classification of the memory cell as a first classification when the threshold voltage is larger than the read reference voltage, or
determining a classification of the memory cell as a second classification when the threshold voltage is smaller than the read reference voltage.

20. The non-transitory medium of claim 19 , wherein the applying the second voltage is applied so as to be equal to the first voltage based on the determined first classification of the memory cell, or as a zero volt

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Luo Zhe
• Li Da
• Xu Feng
• Tian Yaoyao
• Jia Jianquan
• Zhao Xiangnan

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title