Display device with voltage line contact

Patent metadata

Field	Value
Publication number	US-12213359-B2
Application number	US-202318226229-A
Country	US
Kind code	B2
Filing date	Jul 25, 2023
Priority date	Jul 20, 2020
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

A display device includes a first active pattern disposed on a substrate, a first gate electrode disposed on the first active pattern, a second active pattern disposed on the first gate electrode, being electrically connected to the first gate electrode, and including an extension part extending in a first direction and a protrusion part protruding from the extension part in a second direction crossing the first direction, and a voltage line disposed on the second active pattern, extending in the first direction, and overlapping the protrusion part in an overlapping region. The voltage line contacts the protrusion part through a first contact, and the first contact entirely overlaps the overlapping region on a plane.

First claim

What is claimed is:

1. A display device comprising:
a first active pattern disposed on and above a substrate;
a first gate electrode disposed on and above the first active pattern;
a second active pattern disposed on and above the first gate electrode, being electrically connected to the first gate electrode, and constituting a first pixel structure and a second pixel structure adjacent to the first pixel structure; and
a voltage line disposed on and above the first gate electrode and providing a voltage to the first gate electrode through the second active pattern.

2. The display device of claim 1 , wherein a second active pattern includes a first portion and a second portion,
the first portion constitutes the first pixel structure, and
the second portion is connected to the first portion and constitutes the second pixel structure.

3. The display device of claim 2 , wherein a physical layout of the first portion and the second portion are symmetrical to each other as seen in plan view.

4. The display device of claim 1 , further comprising:
a first gate line disposed on the first active pattern and providing a first gate signal to the second active pattern;
an anode initialization voltage line disposed on the first gate line and providing an anode initialization voltage to the first active pattern; and
a data transmission vertical line transmitting a data voltage and overlapping the anode initialization voltage line,
wherein the anode initialization voltage line shields the first gate line from the data transmission vertical line.

5. The display device of claim 4 , further comprising:
a second gate line disposed under the first gate line and providing a second gate signal to the first active pattern,
wherein the anode initialization voltage line further shields the second gate line from the data transmission vertical line.

6. The display device of claim 5 , further comprising:
a data line transmitting the data voltage, disposed in a same layer as the data transmission vertical line, and overlapping the anode initialization voltage line,
wherein the anode initialization voltage line further shields the first and second gate lines from the data line.

7. The display device of claim 4 , wherein the anode initialization voltage line is disposed in a different layer than the voltage line.

8. The display device of claim 1 , wherein the first active pattern includes a silicon semiconductor, and
the second active pattern includes an oxide semiconductor.

9. The display device of claim 1 , wherein the first and second pixel structures provide current to different light emitting diodes.

10. A display device comprising:
a first active pattern disposed on a substrate;
a first gate electrode disposed on the first active pattern:
a second active pattern disposed on the first gate electrode, being electrically connected to the first gate electrode, and constituting a first pixel structure and a second pixel structure adjacent to the first pixel structure;
a voltage line disposed on the first gate electrode and providing a voltage to the first gate electrode through the second active pattern;
a first gate line disposed on the first active pattern and providing a first gate signal to the second active pattern; and
a data transmission horizontal line disposed on the voltage line, transmitting a data voltage, and overlapping the voltage line,
wherein the voltage line shields the first gate line from the data transmission horizontal line.

11. The display device of claim 10 , further comprising:
a data transmission vertical line disposed on the voltage line, transmitting the data voltage, and overlapping the voltage line,
wherein the voltage line further shields the first gate line from the data transmission vertical line.

12. The display device of claim 11 , further comprising:
a data line disposed in a same layer as the data transmission vertical line, transmitting the data voltage, and overlapping the voltage line,
wherein the voltage line further shields the first gate line from the data line.

13. A display device comprising:
a first active pattern disposed on a substrate;
a first gate electrode disposed on the first active pattern;
a second active pattern including an extension part extending in a first direction and a protrusion part protruding from the extension part in a second direction crossing the first direction disposed on the first gate electrode, being electrically connected to the first gate electrode, and constituting a first pixel structure and a second pixel structure adjacent to the first pixel structure; and
a voltage line disposed on the first gate electrode and providing a voltage to the first gate electrode through the second active pattern.

14. The display device of claim 13 , wherein a second active pattern includes a first portion and a second portion,
the first portion constitutes the first pixel structure, and
the second portion is connected to the first portion and constitutes the second pixel structure.

15. The display device of claim 14 , wherein the first portion and the second portion are symmetrical to each other.

16. The display device of claim 12 , further comprising:
a first gate line disposed on the first active pattern and providing a first gate signal to the second active pattern; and
a data transmission horizontal line disposed on the voltage line, transmitting a data voltage, and overlapping the voltage line,
wherein the voltage line shields the first gate line from the data transmission horizontal line.

17. The display device of claim 16 , further comprising:
a data transmission vertical line disposed on the voltage line, transmitting the data voltage, and overlapping the voltage line,
wherein the voltage line further shields the first gate line from the data transmission vertical line.

18. The display device of claim 17 , further comprising:
a data line disposed in a same layer as the data transmission vertical line, transmitting the data voltage, and overlapping the voltage line,
wherein the voltage line further shields the first gate line from the data line.

19. The display device of claim 13 , further comprising:
a first gate line disposed on the first active pattern and providing a first gate signal to the second active pattern;
an anode initialization voltage line disposed on the first gate line and providing an anode initialization voltage to the first active pattern; and
a data transmission vertical line transmitting a data voltage and overlapping the anode initialization voltage line,
wherein the anode initialization voltage line is disposed in a different layer than the voltage line, and
the anode initialization voltage line shields the first are line from the data transmission vertical line.

20. The display device of claim 13 , wherein the first active pattern includes a silicon semiconductor, and
the second active pattern includes an oxide semiconductor.

Assignees

• Samsung Display Co Ltd

Inventors

• Cho Seung-Hwan
• Choi Wonsuk
• Tanaka Tetsuhiro
• Park Jiryun
• Seong Seokje
• Sung Seungwoo
• Lee Jiseon

Classifications

• H10K59/121

  characterised by the geometry or disposition of pixel elements · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10K59/1315

  comprising structures specially adapted for lowering the resistance · CPC title