Display panel and display apparatus with pixel circuits behind light blocking assembly

Patent metadata

Field	Value
Publication number	US-12213339-B2
Application number	US-202217591262-A
Country	US
Kind code	B2
Filing date	Feb 2, 2022
Priority date	Jan 14, 2020
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

A display panel and display apparatus. The display panel includes a first display area, a second display area, and an isolation area. A light transmittance of the first display area is greater than a light transmittance of the second display area. At least a part of the isolation area is positioned between the first display area and the second display area. The display panel includes a plurality of first sub-pixels positioned in the first display area; a first pixel circuit positioned in the second display area, the first pixel circuit being electrically connected to the first sub-pixels in the first display area and being configured to drive the first sub-pixels in the first display area to display; and a light-blocking assembly positioned in the isolation area, the light-blocking assembly being configured to block light incident from the first sub-pixels to the first pixel circuit.

First claim

What is claimed is:

1. A display panel comprising a first display area, a second display area, and an isolation area, a light transmittance of the first display area being greater than a light transmittance of the second display area, and at least a part of the isolation area being positioned between the first display area and the second display area, the display panel comprising:
a plurality of first sub-pixels positioned in the first display area;
a first pixel circuit positioned in the second display area, the first pixel circuit being electrically connected to the first sub-pixels in the first display area and being configured to drive the first sub-pixels in the first display area to display; and
a light-blocking assembly positioned in the isolation area, the light-blocking assembly being configured to block light incident from the first sub-pixels to the first pixel circuit.

2. The display panel of claim 1 , wherein the isolation area is arranged around an entire periphery of the first display area, and an orthographic projection of the light-blocking assembly in a thickness direction of the display panel appears as a closed pattern around the first display area.

3. The display panel of claim 1 , wherein the display panel comprises:
a substrate;
a component layer positioned on the substrate, the first pixel circuit being positioned in the component layer;
a planarization layer positioned on the component layer; and
a pixel-defining layer positioned on the planarization layer;
wherein the light-blocking assembly extends through at least a part of the component layer in a thickness direction of the display panel, and the light-blocking assembly extends through the planarization layer and the pixel-defining layer.

4. The display panel of claim 3 , wherein the component layer comprises a first insulating layer, a second insulating layer, and an interlayer dielectric layer which are stacked, and the first insulating layer is arranged close to the substrate and the interlayer dielectric layer is arranged away from the substrate,
the light-blocking assembly extends to the first insulating layer in the thickness direction of the display panel.

5. The display panel of claim 4 , wherein the first pixel circuit comprises a plurality of thin film transistors, each of the thin film transistors comprises a drain, a source, a gate, and an active layer, the gate is positioned between the first insulating layer and the second insulating layer, and the source and the drain are positioned on the interlayer dielectric layer and contact with the active layer through through-holes in the first insulating layer, the second insulating layer, and the interlayer dielectric layer.

6. The display panel of claim 3 , wherein the first pixel circuit comprises a thin film transistor, the thin film transistor comprises an active layer,
the component layer comprises a limit layer arranged in a same layer with the active layer of the thin film transistor, and
the light-blocking assembly extends from a surface of the pixel-defining layer away from the substrate to a surface of the limit layer away from the substrate.

7. The display panel of claim 6 , wherein the light-blocking assembly comprises:
a first light-blocking unit comprising a first light-blocking portion and a first connecting portion, the first light-blocking portion extending between a surface of the component layer away from the substrate and the surface of the limit layer away from the substrate, and the first connecting portion being connected with the first light-blocking portion and extending along the surface of the component layer away from the substrate; and
a second light-blocking unit extending between the surface of the pixel-defining layer away from the substrate and the first connecting portion.

8. The display panel of claim 7 , wherein the first light-blocking portion and the first connecting portion are formed as an integrated structure.

9. The display panel of claim 7 , wherein the component layer comprises at least one metal layer, and a material of the first light-blocking unit is the same as a material of the metal layer.

10. The display panel of claim 7 , wherein the display panel further comprises a supporting column arranged on the pixel-defining layer; and
the second light-blocking unit is an integrated structure, and a material of the second light-blocking unit is same with a material of the supporting column.

11. The display panel of claim 7 , wherein the second light-blocking unit comprises:
a first light-blocking sub-unit extending between a surface of the planarization layer away from the substrate and the first connecting portion; and
a second light-blocking sub-unit extending between the surface of the pixel-defining layer away from the substrate and the first light-blocking sub-unit.

12. The display panel of claim 11 , wherein the first light-blocking sub-unit comprises a second light-blocking portion and a second connecting portion, the second light-blocking portion extends between the surface of the planarization layer away from the substrate and the first connecting portion, the second connecting portion is connected with the second light-blocking portion and extends along the surface of the planarization layer away from the substrate, and the second light-blocking sub-unit is connected with the second connecting portion.

13. The display panel of claim 12 , wherein an orthographic projection of the first light-blocking portion on the substrate, an orthographic projection of the second light-blocking portion on the substrate, and an orthographic projection of the second light-blocking sub-unit on the substrate do not overlap with each other.

14. The display panel of claim 12 , wherein the second light-blocking portion and the second connecting portion are formed as an integrated structure.

15. The display panel of claim 11 , wherein the display panel further comprises a supporting column arranged on the pixel-defining layer, and a material of the second light-blocking sub-unit is same with a material of the supporting column.

16. The display panel of claim 11 , wherein each of the first sub-pixels comprises a first electrode, a first light-emitting structure on the first electrode, and a second electrode on the first light-emitting structure,
wherein a material of the first light-blocking sub-unit is same with a material of the first electrode.

17. A display apparatus comprising the display panel of claim 1 .

Assignees

• Kunshan Govisionox Optoelectronics Co Ltd

Inventors

• Liu Rusheng
• Wang Guanghui
• Cai Junfei
• Lou Junhui

Classifications

• H10K59/8792

  comprising light absorbing layers, e.g. black layers · CPC title

• H10K50/865 Primary

  comprising light absorbing layers, e.g. light-blocking layers · CPC title

• H10K59/126 Primary

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/122

  Pixel-defining structures or layers, e.g. banks · CPC title