Voltage regulator with pulse frequency control

Patent metadata

Field	Value
Publication number	US-12212237-B2
Application number	US-202217974787-A
Country	US
Kind code	B2
Filing date	Oct 27, 2022
Priority date	Oct 27, 2022
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

The present disclosure describes a system with a first counter circuit, a first converter circuit, a second counter circuit, and a second converter circuit. The first counter circuit is configured to output a first count value based on a comparison between a first reference value and a switched node value of a voltage regulator. The first converter circuit is configured to adjust an activation time of the voltage regulator based on the first count value. The second counter circuit is configured to output a second count value based on a comparison between a second reference value and the switched node value of the voltage regulator. The second converter circuit is configured to adjust an amount of current drawn away from an output of the voltage regulator based on the second count value.

First claim

What is claimed is:

1. A system, comprising:
a first counter circuit configured to output a first count value based on a comparison between a first reference value and a switched node value of a voltage regulator;
a first converter circuit configured to adjust an activation time of the voltage regulator based on the first count value;
a second counter circuit configured to be enabled in response to the first count value reaching a maximum value, wherein the second counter circuit is configured to output a second count value based on a comparison between a second reference value and the switched node value of the voltage regulator; and
a second converter circuit configured to adjust an amount of current drawn away from an output of the voltage regulator based on the second count value.

2. The system of claim 1 , wherein the first reference value is higher than the second reference value.

3. The system of claim 1 , wherein the first reference value is at a first frequency higher than an upper limit of an audio band frequency range and the second reference value is at a second frequency between the first frequency and the upper limit of the audio band frequency range.

4. The system of claim 1 , wherein the first reference value is a frequency value, and wherein the first counter circuit is configured to:
increment the first count value in response to a frequency associated with the switched node value of the voltage regulator being below the frequency value; and
decrement the first count value in response to the frequency associated with the switched node value of the voltage regulator being above the frequency value.

5. The system of claim 1 , wherein the first converter circuit comprises an adjustable RC delay circuit configured to adjust the activation time of the voltage regulator.

6. The system of claim 1 , wherein the first converter circuit is configured to select a minimum delay element in response to the first count value reaching the maximum value.

7. The system of claim 1 , wherein the second reference value is a frequency value, and wherein the second counter circuit is configured to:
increment the second count value in response to a frequency associated with the switched node value of the voltage regulator being below the frequency value; and
decrement the second count value in response to the frequency associated with the switched node value of the voltage regulator being above the frequency value.

8. The system of claim 1 , wherein the second converter circuit comprises an adjustable resistor circuit configured to adjust an amount of current drawn away from the output of the voltage regulator.

9. A system, comprising:
a load circuit; and
a voltage regulator electrically connected to the load circuit, wherein the voltage regulator comprises:
an inductance element; and
a pulse frequency control circuit, comprising:
a first counter circuit configured to output a first count value based on a comparison between a first frequency reference value and a frequency at which a current flows through the inductance element;
a first digital-to-analog converter (DAC) circuit configured to adjust an amount of the current flowing through the inductance element based on the first count value;
a second counter circuit configured to output a second count value based on a comparison between a second frequency reference value and the frequency at which the current flows through the inductance element; and
a second DAC circuit configured to adjust an amount of current drawn away from an output of the voltage regulator based on the second count value.

10. The system of claim 9 , wherein the voltage regulator is a step-up voltage converter, a step-down voltage converter, or a step down/up voltage converter.

11. The system of claim 9 , further comprising:
a logic device configured to receive the first count value from the first counter circuit and to enable the second counter circuit in response to the first count value reaching a maximum value.

12. The system of claim 9 , further comprising:
a first reference signal generator configured to generate the first frequency reference value; and
a second reference signal generator configured to generate the second frequency reference value,
wherein the first frequency reference value is higher than an upper limit of an audio band frequency range and the second frequency reference value is between the first frequency reference value and the upper limit of the audio band frequency range.

13. The system of claim 9 , wherein the first DAC circuit comprises:
an adjustable RC delay circuit;
a control circuit configured to select an RC delay element from the adjustable RC delay circuit based on the first count value; and
a latch circuit configured to transition from a first logic state to a second logic state in an amount of time based on the selected RC delay element.

14. The system of claim 9 , wherein the second DAC circuit comprises:
an adjustable resistor circuit;
a control circuit configured to select a resistance element from the adjustable resistor circuit based on the second count value; and
a current source and resistor combination configured to provide a voltage to the selected resistance element.

15. A method, comprising:
generating a first count value based on a comparison between a first reference value and a switched node value of a voltage regulator;
adjusting an activation time of the voltage regulator based on the first count value;
generating a second count value based on a comparison between a second reference value and the switched node value of the voltage regulator; and
adjusting an amount of current drawn away from an output of the voltage regulator based on the second count value.

16. The method of claim 15 , wherein generating the first count value comprises:
generating a frequency for the first reference value; and
comparing the frequency for the first reference value to a frequency associated with the switched node value of the voltage regulator.

17. The method of claim 15 , wherein adjusting the activation time of the voltage regulator comprises selecting a delay element based on the first count value.

18. The method of claim 15 , wherein generating the second count value comprises enabling a counter circuit in response to the first count value reaching a maximum value.

19. The method of claim 15 , wherein generating the second count value comprises:
generating a frequency for the second reference value; and
comparing the frequency for the second reference value to a frequency associated with the switched node value of the voltage regulator.

20. The method of claim 15 , wherein adjusting the amount of current drawn from the output of the voltage regulator comprises selecting a resistance element based on the second count value.

Assignees

• Apple Inc

Inventors

• Couleur Michael
• Matei Bogdan-Eugen
• Sun Ming
• Suresh Bhanupriya

Classifications

• H03M1/1014

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/804

  with charge redistribution · CPC title

• H03M1/808

  using resistors · CPC title

• H02M1/0032

  Control circuits allowing low power mode operation, e.g. in standby mode · CPC title

• H02M1/14

  Arrangements for reducing ripples from DC input or output · CPC title