Storage device and read recovery method thereof

Patent metadata

Field	Value
Publication number	US-12211565-B2
Application number	US-202318363734-A
Country	US
Kind code	B2
Filing date	Aug 2, 2023
Priority date	Feb 27, 2023
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

Provided is an operation method of a memory controller which includes obtaining first read data from a second external device based on a first read command received from a first external device and performing error correction and decoding on the first read data to determine whether reading is successful or unsuccessful, performing a hard decoding-based read recovery operation and a soft decoding-based read recovery operation when a read failure occurs as a result of the first read operation, determining whether there is a second read command queued when the hard decoding-based read recovery has failed, temporarily stopping the read recovery operation for the first read data when there is the second read command queued and obtaining second read data by reading data from the second external device based on the second read command and performing error correction and decoding on the second read data.

First claim

What is claimed is:

1. An operation method of a memory controller, the operation method comprising:
a first read operation of obtaining first read data from a second external device based on a first read command received from a first external device and performing error correction and decoding on the first read data to determine whether the first read operation is successful or unsuccessful;
a first read recovery operation of performing a hard decoding-based read recovery operation and a soft decoding-based read recovery operation when the first read operation is determined to be unsuccessful;
an operation of determining whether there is a second read command queued when the hard decoding-based read recovery operation has failed;
an operation of temporarily stopping the first read recovery operation when there is the second read command queued; and
a second read operation of obtaining second read data from the second external device based on the second read command and performing the error correction and decoding on the second read data.

2. The operation method of claim 1 , further comprising performing the soft decoding-based read recovery operation by resuming the first read recovery operation after the second read operation is successful.

3. The operation method of claim 2 , further comprising an operation of resuming, in a case where an abort command for the first read command is received while the first read recovery operation is temporarily stopped, the first read recovery operation when the memory controller is in an idle state.

4. The operation method of claim 1 , further comprising:
performing, after the second read operation is successful and when there are read commands queued, a third read operation according to each of third read commands queued until the third read commands queued have been processed; and
performing the soft decoding-based read recovery operation by resuming the first read recovery operation after the read operation according to each of the read commands queued have been processed.

5. The operation method of claim 1 , wherein the hard decoding-based read recovery operation comprises at least one of a history read operation, a hard read retry operation, and an eBoost operation.

6. The operation method of claim 1 , wherein the hard decoding-based read recovery operation comprises an adjacent word line-based read operation of:
providing, to the second external device, as information of a read voltage for the first read operation, information of a second read voltage which has applied to a second word line adjacent to a first word line of a page to be read in the first read operation; and
obtaining the first read data from the second external device.

7. The operation method of claim 1 , wherein the hard decoding-based read recovery operation comprises an adjacent page-based read operation of:
providing, to the second external device, as information of a read voltage for the first read operation, information of a third read voltage which has been used in reading a page adjacent to a page to be read in the first read operation; and
obtaining the first read data from the second external device.

8. A memory controller comprising:
a controller configured to:
perform a first read operation of obtaining first read data from a second external device based on a first read command received from a first external device, and performing error correction and decoding on the first read data to determine whether the first read operation is successful or unsuccessful;
perform a hard decoding-based read recovery operation for recovering the first read data when the first read operation is determined to be unsuccessful;
determine whether there is a second read command queued when the hard decoding-based read recovery operation fails; and
perform a second read operation of obtaining, when there is the second read command queued, second read data from the second external device based on the second read command and performing the error correction and decoding on the second read data without performing a soft decoding-based read recovery operation for recovering the first read data.

9. The memory controller of claim 8 , wherein the controller is further configured to perform the soft decoding-based read recovery operation after the second read operation is successful.

10. The memory controller of claim 8 , wherein the controller is further configured to:
perform, after the second read operation is successful and when there are read commands queued, a third read operation according to each of the read commands queued until the read commands queued have been processed; and
perform the soft decoding-based read recovery operation after the third read operation according to each of the read commands queued have been processed.

11. The memory controller of claim 8 , wherein the controller is configured to perform, as the hard decoding-based read recovery operation, at least one of:
an adjacent word line-based read operation of providing, to the second external device, as information of a read voltage for the first read operation, information of a second read voltage which has applied to a second word line adjacent to a first word line of a page to be read and obtaining the first read data from the second external device; and
an adjacent page-based read operation of providing, to the second external device, as information of a read voltage for the first read operation, information of a third read voltage which has been used in reading a page adjacent to a page to be read and obtaining the first read data from the second external device.

12. A storage device comprising:
a memory configured to receive information of a read voltage, determine values of data recorded in memory cells based on the read voltage and provide the data; and
a memory controller configured to:
perform a first read operation of obtaining first read data from the memory based on a first read command received from an external device, and performing error correction and decoding on the first read data to determine whether the first read operation is successful or unsuccessful;
perform a hard decoding-based read recovery operation for recovering the first read data when the first read operation is determined to be unsuccessful;
determine whether there is a second read command queued when the hard decoding-based read recovery fails;
perform a second read operation of obtaining, when there is the second read command queued, second read data from the memory based on the second read command and performing the error correction and decoding on the second read data without performing a soft decoding-based read recovery operation for recovering the first read data.

13. The storage device of claim 12 , wherein the memory controller is further configured to perform the soft decoding-based read recovery operation after the second read operation is successful.

14. The storage device of claim 12 , wherein the memory controller is configured to:
perform, after the second read operation is successful and when there are read commands queued, a third read operation according to each of the read commands queued until the read commands queued have been processed; and
perform the soft decoding-based read recovery operation after the third read operation according to each of the read commands queued have been processed.

15. The storage device of claim 12 , wherein the memory controller is configured to perform, as the hard decoding-based read recovery operation, at least one of:
an adjacent word line-based read operation of providing, to the

Assignees

• Sk Hynix Inc

Inventors

• Jang In Jong

Classifications

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/141

  for bus or memory accesses · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2212/1016

  Performance improvement · CPC title