Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12211452-B2
Application number	US-202318572742-A
Country	US
Kind code	B2
Filing date	May 31, 2023
Priority date	Jun 9, 2022
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

The display substrate includes a shift register arranged on a base substrate, and the shift register includes a plurality of stages of driving circuits; a plurality of stages of the driving circuit are provided in the driving circuit area of the base substrate; a stage of driving circuit area includes a first area and a second area, and the first area is provided with a first type of transistor included in the driving circuit, a second type of transistor included in the driving circuit is provided in the second area; one side of the first area is a side of the power line away from the second area, and the other side of the first area is a side close to the second area of an active layer of the first type of transistor close to the second area.

First claim

What is claimed is:

1. A display substrate, comprising a shift register arranged on a base substrate, wherein the shift register includes a plurality of stages of driving circuits; the driving circuit includes a first input circuit, a second input circuit, a first output circuit and a control circuit; the first output circuit is configured to provide a first scanning driving signal to a first driving signal output terminal under the control of a potential of a first node and a potential of a second node; the first input circuit is configured to input a signal to a third node under the control of a clock signal; the second input circuit is configured to input a signal provided by a power line to the second node under the control of a potential of the third node; the control circuit is configured to control the potential of the third node and the potential of the first node;
a plurality of stages of driving circuits are provided in a driving circuit area of the base substrate; wherein a stage of driving circuit area includes a first area and a second area, and a first type of transistor included in the driving circuit is arranged in the first area, a second type of transistor included in the driving circuit is arranged in the second area;
one side of the first area is a side of the power line away from the second area, and the other side of the first area is a side close to the second area of an active layer of the first type of transistor close to the second area;
one side of the second area is a side of the power line away from the first area, and the other side of the second area is the side close to the second area of the active layer of the first type of transistor close to the second area.

2. The display substrate according to claim 1 , wherein the power line includes a first power line; the second input circuit is configured to input a first voltage signal provided by a first power line into the second node under the control of the potential of the third node;
X 1/ X 3≥0.21;

wherein, X 1 is a width of the first area in a first direction, and X 3 is a width of the second area in the first direction;
the first direction is a direction intersecting an extending direction of the first power line.

3. The display substrate according to claim 2 , wherein the second input circuit includes a first transistor; a gate electrode of the first transistor is electrically connected to the third node, and a first electrode of the first transistor is electrically connected to the second power line, a second electrode of the first transistor is electrically connected to the second node; the first transistor is a first type of transistor;
WT 1/ X 1≥0.258;

wherein, WT 1 is a width of an active layer of the first transistor along the first direction.

4. The display substrate according to claim 1 , wherein the power line includes a second power line; the second input circuit is configured to input a second voltage signal provided by a second power line to the second node under the control of the potential of the third node;
X 1/ X 3≥0.52;

wherein, X 1 is a width of the first area in a first direction, and X 3 is a width of the second area in the first direction;
the first direction is a direction intersecting an extension direction of the second power line.

5. The display substrate according to claim 4 , wherein the first type of transistor is an N-type transistor, and the second type of transistor is a P-type transistor;
a distance between at least one of the N-type transistors and the second power line is smaller than a distance between the P-type transistor and the second power line.

6. The display substrate according to claim 4 , wherein the driving circuit further includes a second output circuit, and the second output circuit is configured to control the second driving signal output terminal to output the second scanning driving signal under the control of the potential of the third node; the second output circuit includes a second transistor; a gate electrode of the second transistor is electrically connected to the third node, and a first electrode of the second transistor is electrically connected to the second power line, a second electrode of the second transistor is electrically connected to the second driving signal output terminal; the second transistor is a first type of transistor;
WT 2/ X 1≥0.33;

WT 2 is a width of the active layer of the second transistor along the first direction;
or
wherein the second input circuit includes a first transistor; a gate electrode of the first transistor is electrically connected to the third node, and a first electrode of the first transistor is electrically connected to the second power line, a second electrode of the first transistor is electrically connected to the second node; the driving circuit also includes a second output circuit, the second output circuit is configured to control the second driving signal output terminal to output a second scanning driving signal under the control of the potential of the third node; the second output circuit includes a second transistor; a gate electrode of the second transistor is electrically connected to the third node, and a first electrode of the second transistor is electrically connected to the second power line, and a second electrode of the second transistor is electrically connected to the second driving signal output terminal; both the first transistor and the second transistor are first type of transistors;
WT 2/ WT 1≥3.25;

the width of the active layer of the first transistor along the first direction is WT 1 , and WT 2 is the width of the active layer of the second transistor along the first direction.

7. The display substrate according to claim 1 , wherein the display substrate further includes a clock signal line group arranged in a driving circuit area, the clock signal line group is configured to provide the clock signal;
an active layer of at least one first type of transistor is located between the clock signal line group and the power line in the first direction;
an overlapping area between an orthographic projection of the active layer of at least one first type of transistor on the base substrate and an orthographic projection of the power line on the base substrate is less than or equal to five-sixth of an area of the active layer of the at least one first type of transistor.

8. The display substrate according to claim 1 , wherein a ratio of a length of the active layer of at least one first type of transistor along the second direction to a height of the driving circuit is less than or equal to 0.75.

9. The display substrate according to claim 1 , wherein the display substrate further includes a first active layer arranged in the second area; the first active layer includes a first active portion, two second active portions, and two third active portions; the display substrate further includes a second output circuit;
the first active portion serves as an active layer of a third transistor, the two second active portions serve as an active layer of a fourth transistor, and the two third active portions serve as an active layer of a fifth transistor;
the third transistor is a transistor included in the first output circuit that outputs a first voltage signal, the fifth transistor is a transistor included in the first output circuit that outputs a clock signal, and the fourth transistor is a transistor included in the second output circuit that outputs a third voltage signal;
a channel area of an nth transistor is ARn, ARn≥2 (n-1) i, where n is equal to 1, 2 or 3, and i is an unit channel area.

10. The display substrate according to claim 9 , wherein an area P 1 of

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Liu Miao
• Hao Xueguang
• Liu Libin
• Chen Teng
• Wu Xinyin
• Qiao Yong
• Yao Xing
• Wang Jingquan

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title