Shift register circuit and driving method thereof, gate driving circuit, and display device

Patent metadata

Field	Value
Publication number	US-12211447-B2
Application number	US-202117765045-A
Country	US
Kind code	B2
Filing date	Mar 23, 2021
Priority date	Mar 23, 2021
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

A shift register circuit includes a first control sub-circuit and a first output sub-circuit. The first control sub-circuit is configured to: adjust a voltage of a first node to a turn-on voltage due to an influence of a first direct current voltage signal from a first clock signal terminal, an initial voltage signal from an initial signal terminal and a second direct current voltage signal from a second clock signal terminal; and maintain the voltage of the first node at the turn-on voltage due to an influence of a first clock signal from the first clock signal terminal and a second clock signal from the second clock signal terminal. The first output sub-circuit is configured to be turned on under a control of the turn-on voltage of the first node to transmit a first voltage signal from a first voltage terminal to a signal output terminal.

First claim

What is claimed is:

1. A shift register circuit, comprising:
a first control sub-circuit coupled to a first clock signal terminal, a second clock signal terminal, an initial signal terminal and a first node; the first control sub-circuit being configured to:
adjust a voltage of the first node to a turn-on voltage due to an influence of a first direct current voltage signal from the first clock signal terminal, an initial voltage signal from the initial signal terminal and a second direct current voltage signal from the second clock signal terminal; and
maintain the voltage of the first node at the turn-on voltage due to an influence of a first clock signal from the first clock signal terminal and a second clock signal from the second clock signal terminal;

a first output sub-circuit coupled to the first node, a first voltage terminal and a signal output terminal;
the first output sub-circuit being configured to be turned on under a control of the turn-on voltage of the first node to transmit a first voltage signal from the first voltage terminal to the signal output terminal;
a second control sub-circuit coupled to the first node, the first voltage terminal, a first control signal terminal, a second control signal terminal, a fourth clock signal terminal, a second voltage terminal, a second node and the first control sub-circuit;
the second control sub-circuit being configured to:
under a control of a first control signal from the first control signal terminal and a second control signal from the second control signal terminal, and due to an influence of the first voltage signal from the first voltage terminal and a fourth clock signal from the fourth clock signal terminal, adjust a voltage of the second node to a turn-on voltage; and
transmit the first voltage signal from the first voltage terminal to the first control sub-circuit under a control of the first control signal from the first control signal terminal; and

a second output sub-circuit coupled to the second node, the second voltage terminal and the signal output terminal;
the second output sub-circuit being configured to:
be turned on under a control of the turn-on voltage of the second node to transmit a second voltage signal from the second voltage terminal to the signal output terminal;

wherein the first control sub-circuit includes:
a holding unit coupled to the first clock signal terminal, the first node and the initial signal terminal;
the holding unit being configured to:
be turned off due to an influence of the first direct current voltage signal from the first clock signal terminal and the initial voltage signal from the initial signal terminal; and
be turned on under a control of the first clock signal from the first clock signal terminal and due to an influence of the second clock signal from the second clock signal terminal, so as to maintain the voltage of the first node at the turn-on voltage; and

a first control unit coupled to the second clock signal terminal and the first node;
the first control unit being configured to:
adjust the voltage of the first node to the turn-on voltage due to an influence of the second direct current voltage signal from the second clock signal terminal; and
adjust the voltage of the first node due to the influence of the second clock signal from the second clock signal terminal.

2. The shift register circuit according to claim 1 , wherein the holding unit includes:
a first transistor, a control electrode of the first transistor being coupled to the first clock signal terminal, a first electrode of the first transistor being coupled to the initial signal terminal, and a second electrode of the first transistor being coupled to the first node;
the first control unit includes:
a first capacitor, a first terminal of the first capacitor being coupled to the second clock signal terminal, and a second terminal of the first capacitor being coupled to the first node.

3. The shift register circuit according to claim 1 , wherein the first control sub-circuit further includes:
a first anti-leakage unit coupled to the first voltage terminal;
the holding unit being coupled to the first node through the first anti-leakage unit;
the first anti-leakage unit being configured to maintain the turn-on voltage of the first node under a control of the first voltage signal from the first voltage terminal and due to an influence of the turn-on voltage of the first node.

4. The shift register circuit according to claim 3 , wherein the first anti-leakage unit includes:
an eleventh transistor, a control electrode of the eleventh transistor being coupled to the first voltage terminal, a first electrode of the eleventh transistor being coupled to the first node, and a second electrode of the eleventh transistor being coupled to the holding unit.

5. The shift register circuit according to claim 1 , wherein the first control sub-circuit further includes:
a second control unit coupled to the holding unit, the second control sub-circuit, the fourth clock signal terminal and the second voltage terminal;
the second control unit being configured to transmit the second voltage signal from the second voltage terminal to the holding unit under a control of the fourth clock signal from the fourth clock signal terminal and the second control sub-circuit.

6. The shift register circuit according to claim 5 , wherein the second control unit includes:
a second transistor, a control electrode of the second transistor being coupled to the second control sub-circuit, and a first electrode of the second transistor being coupled to the second voltage terminal; and
a third transistor, a control electrode of the third transistor being coupled to the fourth clock signal terminal, a first electrode of the third transistor being coupled to a second electrode of the second transistor, and a second electrode of the third transistor being coupled to the holding unit.

7. The shift register circuit according to claim 5 , wherein the second control sub-circuit includes a third control unit, a fourth control unit, an adjustment unit and a fifth control unit, wherein the third control unit is coupled to the holding unit, the second control unit, the first control signal terminal, the fourth control unit, the adjustment unit and the first voltage terminal;
the third control unit is configured to transmit the first voltage signal from the first voltage terminal to the second control unit and the fourth control unit under the control of the first control signal from the first control signal terminal;
the fourth control unit is further coupled to the fourth clock signal terminal and a third node;
the fourth control unit is configured to transmit the fourth clock signal from the fourth clock signal terminal to the third node under a control of the first voltage signal output from the third control unit;
the adjustment unit is further coupled to the third node;
the adjustment unit is configured to adjust a control voltage of the fourth control unit according to a voltage of the third node; and
the fifth control unit is coupled to the first node, the second node, the third node, the second voltage terminal and the second control signal terminal; the fifth control unit is configured to:
transmit the voltage of the third node to the second node under a control of the second control signal from the second control signal terminal; and
transmit the second voltage signal from the second voltage terminal to the second node under the control of the turn-on voltage of the first node.

8. The shift register circuit according to claim 7 , wherein the third control unit includes:
a fourth transistor, a control electrode of the fourth transistor being coupled to the first con

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shang Guangliang
• Lu Jiangnan
• Han Long
• Wang Li
• Liu Libin
• Yin Xinshe
• Shi Shiming

Classifications

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title