Memory system including nonvolatile memory and method of controlling the same

Patent metadata

Field	Value
Publication number	US-12210450-B2
Application number	US-202318463396-A
Country	US
Kind code	B2
Filing date	Sep 8, 2023
Priority date	Sep 16, 2022
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

According to one embodiment, in response to restoration of power to a memory system, a controller in the memory system notifies a host that the memory system is ready. When an input/output command specifying a logical address belonging to a logical address range is received, the controller selects a block corresponding to the logical address range and rebuilds, based on address translation information and an update log which are stored in the selected block, the latest address translation information corresponding to the logical address range. The controller updates the rebuilt latest address translation information, based on a list of logical addresses corresponding to lost write data, stored in the selected block.

First claim

What is claimed is:

1. A memory system connectable to a host, the memory system comprising:
a nonvolatile memory including a plurality of blocks;
a volatile memory; and
a controller configured to manage address translation information indicating a correspondence between each of logical addresses in a logical address space of the memory system and each of physical addresses of the nonvolatile memory, using a logical-to-physical address translation table stored in the volatile memory, wherein
the controller is configured to:
divide the logical-to-physical address translation table into a plurality of table areas including at least a first table area corresponding to a first logical address range and a second table area corresponding to a second logical address range;
periodically perform first processing of writing, into a first block among the plurality of blocks, address translation information on the first table area acquired from the volatile memory and an update log indicating an update content of the address translation information on the first table area updated after acquisition of the address translation information on the first table area;
periodically perform second processing of writing, into a second block among the plurality of blocks, address translation information on the second table area acquired from the volatile memory and an update log indicating an update content of the address translation information on the second table area updated after acquisition of the address translation information on the second table area;
save, into the first block and the second block, a first list indicating a list of logical addresses corresponding to first write data lost due to unexpected power loss among write data to be written into the first logical address range and a second list indicating a list of logical addresses corresponding to second write data lost due to the unexpected power loss among write data to be written into the second logical address range, respectively;
in response to restoration of power to the memory system,
notify the host that the memory system is ready to process an input/output command;
when an input/output command specifying a logical address belonging to one logical address range of the first logical address range and the second logical address range is received from the host,
select a block corresponding to the one logical address range from the first block and the second block, and rebuild, onto the volatile memory, based on the address translation information on the table area stored in the selected block and the update log of the address translation information, stored in the selected block, latest address translation information on a table area corresponding to the one logical address range; and
when a list of logical addresses corresponding to the lost write data is stored in the selected block, update, based on the list in the selected block, the rebuilt latest address translation information such that a value indicating an error is associated with each of the logical addresses corresponding to the lost write data.

2. The memory system according to claim 1 , wherein
the controller is configured to:
in response to occurrence of the unexpected power loss, save the first list and the second list into the first block and the second block, respectively, by writing the first list and the second list into the first block and the second block, respectively, using power stored in a capacitor of the memory system.

3. The memory system according to claim 1 , wherein
the controller is configured to:
in response to occurrence of the unexpected power loss, write both the first list and the second list into a predetermined block of the nonvolatile memory, using power stored in a capacitor of the memory system; and
in response to restoration of the power to the memory system, save the first list and the second list into the first block and the second block, respectively, by copying the first list and the second list from the predetermined block to the first block and the second block, respectively.

4. The memory system according to claim 1 , wherein
the controller is configured to:
manage the update log indicating the update content of the address translation information on the first table area and the update log indicating the update content of the address translation information on the second table area, respectively, using a first log buffer and a second log buffer stored in the volatile memory;
in response to occurrence of the unexpected power loss,
when an unsaved update log which is not saved into the first block is present in the first log buffer, write the unsaved update log of the first log buffer into the first block, using power stored in a capacitor of the memory system; and
when an unsaved update log which is not saved into the second block is present in the second log buffer, write the unsaved update log of the second log buffer into the second block, using the power stored in the capacitor.

5. The memory system according to claim 1 , wherein
the logical-to-physical address translation table includes a plurality of pieces of address translation information,
the first table area includes at least first address translation information and second address translation information among the pieces of address translation information,
the second table area includes at least third address translation information and fourth address translation information among the plurality of pieces of address translation information, and
the controller is configured to:
periodically perform the first processing by repeatedly performing processing of acquiring the first address translation information from the volatile memory; processing of writing, into the first block, the first address translation information and a first update log indicating an update content regarding all the address translation information on the first table area updated after acquisition of the first address translation information; processing of acquiring the second address translation information from the volatile memory; and processing of writing, into the first block, the second address translation information and a second update log indicating an update content regarding all the address translation information on the first table area updated after acquisition of the second address translation information; and
periodically perform the second processing by repeatedly performing processing of acquiring the third address translation information from the volatile memory; processing of writing, into the second block, the third address translation information and a third update log indicating an update content regarding all the address translation information on the second table area updated after acquisition of the third address translation information; processing of acquiring the fourth address translation information from the volatile memory; and processing of writing, into the second block, the fourth address translation information and a fourth update log indicating an update content regarding all the address translation information on the second table area updated after acquisition of the fourth address translation information.

6. The memory system according to claim 5 , wherein
the controller is configured to:
in rebuilding the first table area onto the volatile memory,
copy, from the first block to the volatile memory, latest second address translation information in the second address translation information stored in the first block and latest first address translation information in the first address translation information stored in the first block;
reflect, to the latest first address translation information on the volatile memory, a content of a latest first update

Assignees

• Kioxia Corp

Inventors

• Kanno Shinichi
• Tran Aurelien Nam Phong
• Sasaki Yuki

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0617

  in relation to availability · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title