Managing regions of a memory system

Patent metadata

Field	Value
Publication number	US-12210447-B2
Application number	US-202117629306-A
Country	US
Kind code	B2
Filing date	Mar 16, 2021
Priority date	Mar 16, 2021
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

Methods, systems, and devices for managing regions of a memory system are described. A memory system may include a non-volatile memory device and may receive a host performance booster (HPB) command (e.g., a read command) associated with one or more regions of the non-volatile memory device. The memory system may determine whether the region(s) associated with the HPB command are active. In instances where one or more of the associated regions are inactive, the memory system may activate the region(s) and deactivate one or more other regions based on a recency parameter (e.g., a timing parameter). The memory system may process the received HPB command based on the associated region(s) being active.

First claim

What is claimed is:

1. A memory system, comprising:
one or more non-volatile memory devices; and
processing circuitry coupled with the one or more non-volatile memory devices, wherein the processing circuitry is configured to cause the memory system to:
initiate a timer corresponding to a first region in response to performing one or more access operations for data stored at the first region;
determine whether a first recency parameter associated with the first region of the one or more non-volatile memory devices satisfies a threshold, wherein the first recency parameter is based at least in part on a value of the timer;
transmit, to a host system, a first portion of a mapping that indicates relationships between logical addresses and physical addresses of the one or more non-volatile memory devices in the first region based at least in part on determining that the first recency parameter associated with the first region of the one or more non-volatile memory devices satisfies the threshold;
receive a read command to read data that is stored in the first region and a second region of the one or more non-volatile memory devices, the read command comprising a physical address of the one or more non-volatile memory devices from the first portion of the mapping; and
transmit, to the host system, a second portion of the mapping that indicates relationships between logical addresses and physical addresses of the one or more non-volatile memory devices in the second region based at least in part on determining that the first recency parameter associated with the first region of the one or more non-volatile memory devices satisfies the threshold, a second recency parameter associated with the second region of the one or more non-volatile memory devices satisfies the threshold, and receiving the read command.

2. The memory system of claim 1 , wherein to determine whether the first recency parameter satisfies the threshold, the processing circuitry is further configured to cause the memory system to:
determine whether an index associated with the first region is greater than an index threshold in a ranking of regions indicating which regions were accessed most recently.

3. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
determine, for each of a plurality of regions of the one or more non-volatile memory devices, a respective recency parameter, wherein the respective recency parameters comprise a duration elapsed since performing an access operation on the respective region of the plurality of regions and the plurality of regions of the one or more non-volatile memory devices include the first region.

4. The memory system of claim 3 , wherein the processing circuitry is further configured to cause the memory system to:
determine the second recency parameter associated with the second region based at least in part on receiving the read command;
determine that the first recency parameter satisfies the threshold by determining that an access operation was performed on the first region of the one or more non-volatile memory devices within a duration; and
determine that the second recency parameter satisfies the threshold by determining that an access operation was performed on the second region of the one or more non-volatile memory devices within the duration, wherein transmitting the second portion of the mapping to the host system is based at least in part on determining that the second recency parameter satisfies the threshold by determining that the access operation was performed on the second region of the one or more non-volatile memory devices within the duration.

5. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
perform a read operation on the second region of the one or more non-volatile memory devices based at least in part on receiving the read command.

6. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
identify that the physical address included in the read command is in the first region of the one or more non-volatile memory devices based at least in part on receiving the read command.

7. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
activate the first region to use as part of a host performance booster mode, wherein transmitting the first portion of the mapping is part of activating the first region to use as part of the host performance booster mode.

8. The memory system of claim 7 , wherein the processing circuitry is further configured to cause the memory system to:
deactivate the first region from being part of the host performance booster mode based at least in part on determining that the first recency parameter associated with the first region does not satisfy the threshold; and
transmit, to the host system, an indication that the first region of the one or more non-volatile memory devices is deactivated and a third region of the one or more non-volatile memory devices is activated.

9. The memory system of claim 8 , wherein the processing circuitry is further configured to cause the memory system to:
activate the third region of the one or more non-volatile memory devices to use as part of the host performance booster mode based at least in part on deactivating the first region of the one or more non-volatile memory devices; and
perform a second read operation on at least the third region of the one or more non-volatile memory devices based at least in part on activating the third region of the one or more non-volatile memory devices.

10. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
maintain the first region as an active region based at least in part on determining that the first recency parameter associated with the first region of the one or more non-volatile memory devices satisfies the threshold.

11. The memory system of claim 1 , wherein the first region comprises a first quantity of data and is associated with a first quantity of logical block addresses (LBAs) and the second region comprises the first quantity of data and is associated with the first quantity of LBAs.

12. The memory system of claim 1 , wherein the read command comprises a performance booster mode command.

13. A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:
initiate a timer corresponding to a first region in response to performing one or more access operations for data stored at the first region;
determine whether a first recency parameter associated with the first region of a non-volatile memory device satisfies a threshold, wherein the first recency parameter is based at least in part on a value of the timer;
transmit, to a host system, a first portion of a mapping that indicates relationships between logical addresses and physical addresses of the non-volatile memory device in the first region based at least in part on determining that the first recency parameter associated with the first region of the non-volatile memory device satisfies the threshold;
receive a read command to read data that is stored in the first region and a second region of the non-volatile memory device, the read command comprising a physical address of the non-volatile memory device from the first portion of the mapping; and
transmit, to the host system, a second portion of the mapping that indicates relatio

Assignees

• Micron Technology Inc

Inventors

• Zhao Bin
• Wang Lingyun

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title