Lockup detection circuit for an eUSB repeater

Patent metadata

Field	Value
Publication number	US-12210404-B2
Application number	US-202218073510-A
Country	US
Kind code	B2
Filing date	Dec 1, 2022
Priority date	Dec 1, 2022
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

Embodiments of a method and a device of lockup detection for an eUSB repeater are described. In an embodiment, the method involves detecting received data at an analog receiver on a first side of the eUSB repeater, detecting an enable signal for an analog transmitter on a second side of the eUSB repeater, detecting an idle condition of the analog receiver on the first side of the eUSB repeater after detecting the enable signal, setting a timer, determining that the timer has elapsed, and resetting the eUSB repeater after the timer has elapsed while an idle condition is detected on the first side and the enable signal is detected on the second side of the eUSB repeater.

First claim

What is claimed is:

1. A method of lockup detection for an eUSB repeater, the method comprising:
detecting received data at an analog receiver on a first side of the eUSB repeater;
detecting an enable signal for an analog transmitter on a second side of the eUSB repeater;
detecting an idle condition of the analog receiver on the first side of the eUSB repeater after detecting the enable signal;
setting a timer;
determining that the timer has elapsed; and
resetting the eUSB repeater after the timer has elapsed while an idle condition is detected on the first side and the enable signal is detected on the second side of the eUSB repeater.

2. The method of claim 1 , wherein detecting an idle condition comprises detecting that two input lines to the analog receiver are both low.

3. The method of claim 1 , wherein detecting an idle condition comprises detecting that an Idle “J” is present on two input lines to the analog receiver.

4. The method of claim 1 wherein detecting an idle condition comprises detecting that an input line to the analog receiver is high and another input line to the analog receiver is low.

5. The method of claim 1 , further comprising determining a speed mode of the eUSB repeater and detecting an idle condition based on the speed mode.

6. The method of claim 1 , further comprising resetting the timer whenever the idle condition is not present on the first side of the eUSB repeater.

7. The method of claim 1 , wherein the timer has a duration of at least 10 USB Low Speed Unit Intervals (UI).

8. The method of claim 1 , wherein determining that the timer has elapsed comprises detecting that the enable signal is active for a duration of the timer.

9. The method of claim 1 , wherein determining that the timer has elapsed comprises detecting that the analog receiver is receiving an SE0 idle (eUSB) or a J (USB) for a duration of the timer.

10. The method of claim 1 , further comprising:
generating a possible lockup signal when the idle condition is detected and the enable signal is detected; and
applying the possible lockup signal to a counter,
wherein determining that the timer has elapsed comprises determining that the counter has incremented to reach a pre-configured count.

11. The method of claim 1 , wherein resetting the eUSB repeater comprises applying reset signals to state elements of the eUSB repeater that control the data signals of the eUSB repeater.

12. The method of claim 11 , wherein resetting the eUSB repeater comprises applying reset signals to state elements of the eUSB repeater that control the control signals of the eUSB repeater.

13. The method of claim 1 , wherein resetting the eUSB repeater comprises applying reset signals to flip-flops of the eUSB repeater that determine an end of packet.

14. A lockup detection circuit for an eUSB repeater, the circuit comprising:
a first logic gate coupled to an analog receiver of the eUSB repeater to generate an idle signal upon detecting an idle condition of an input of the analog receiver;
an AND gate coupled to the first logic gate and to an analog transmitter of the eUSB repeater to receive an enable signal, the AND gate to generate a possible lockup signal upon receiving the idle signal and the enable signal;
a timer coupled to the possible lockup signal, the timer being started in response to the possible lockup signal; and
a second logic gate to reset the eUSB repeater after the timer has elapsed while the idle condition is detected and the enable signal is detected.

15. The circuit of claim 14 , wherein the analog receiver is coupled to two input lines of a first bus and wherein the first logic gate detects the idle condition upon detecting that the two input lines are both low.

16. The circuit of claim 14 , wherein the first logic gate is coupled to a mode selector signal to indicate a low speed mode or a full speed mode, the first logic gate being configured to generate the idle signal in response to the mode selector signal and upon detecting an idle condition of an input of the analog receiver.

17. An eUSB repeater comprising:
an analog receiver coupled to a first bus;
an analog transmitter coupled to a second bus having an enable signal that is active when the analog transmitter is active;
repeating mode logic between the analog receiver and the analog transmitter to repeat data received on the first bus through the analog receiver to the second bus through the analog transmitter; and
a lockup detection circuit having a first logic gate coupled to the analog receiver to generate an idle signal upon detecting an idle condition of the analog receiver, an AND gate coupled to the first logic gate and to the analog transmitter to receive the enable signal, the AND gate to generate a possible lockup signal upon receiving the idle signal and the enable signal, a timer coupled to the possible lockup signal, the timer being started in response to the possible lockup signal, and a second logic gate coupled to the repeating mode logic to reset the repeating mode logic after the timer has elapsed.

18. The repeater of claim 17 , wherein the second logic gate is further coupled to the timer to reset the timer after the timer has elapsed.

19. The repeater of claim 17 , wherein the repeating mode logic comprises a state element configured to control signal paths through the repeating mode logic and wherein the second logic gate is coupled to the state element to clear the state of the state element.

20. The repeater of claim 17 , wherein the lockup detection circuit further comprises:
a first detection logic gate coupled to input lines of the analog receiver and configured to generate a first idle signal in response to a first mode of the first bus, the first idle signal being coupled to the first logic gate; and
a second detection logic gate coupled to the input lines of the analog receiver and configured to generate a second idle signal in response to a second mode of the first bus,
wherein the first logic gate is coupled to a mode selector signal and selects the first idle signal or the second idle signal as the idle signal in response to the mode selector signal.

Assignees

• Nxp Usa Inc

Inventors

• Jaramillo Kenneth

Classifications

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• G06F11/3027

  where the computing system component is a bus · CPC title

• G06F11/1441 Primary

  Resetting or repowering · CPC title

• G06F11/1443

  Transmit or communication errors · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title