Comparator-based switched-capacitor circuit

Patent metadata

Field	Value
Publication number	US-12206431-B2
Application number	US-202318119311-A
Country	US
Kind code	B2
Filing date	Mar 9, 2023
Priority date	Mar 22, 2022
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

A comparator-based switched-capacitor circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes an analog-to-digital converter (ADC), a decoder, and a switch-capacitor network. The ADC is coupled to the first input terminal and the second input terminal and includes a plurality of comparators. The decoder is coupled to the ADC. The switch-capacitor network includes a comparator, a first current source, a second current source, a plurality of switches, and a plurality of capacitors. The first current source is coupled to the comparator and the first output terminal. The second current source is coupled to the comparator and the second output terminal. The voltage of the first output terminal and the voltage of the second output terminal do not exceed a target range.

First claim

What is claimed is:

1. A comparator-based switched-capacitor (SC) circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the comparator-based SC circuit comprising:
a comparator;
an analog-to-digital converter (ADC) coupled to the first input terminal and the second input terminal;
a decoder coupled to the ADC;
a first switch;
a second switch;
a third switch;
a fourth switch;
a fifth switch;
a sixth switch;
a seventh switch;
an eighth switch;
a ninth switch;
a tenth switch;
a first current source coupled to the comparator and the first output terminal;
a second current source coupled to the comparator and the second output terminal;
a first capacitor having a first end and a second end, the first end being coupled to the first input terminal through the first switch and coupled to the first output terminal through the fourth switch, and the second end being coupled to the comparator and coupled to a reference voltage through the third switch;
a second capacitor having a third end and a fourth end, the third end being coupled to the first input terminal through the second switch and coupled to the decoder through the fifth switch, and the fourth end being coupled to the comparator and coupled to the reference voltage through the third switch;
a third capacitor having a fifth end and a sixth end, the fifth end being coupled to the second input terminal through the sixth switch and coupled to the second output terminal through the ninth switch, and the sixth end being coupled to the comparator and coupled to the reference voltage through the eighth switch; and
a fourth capacitor having a seventh end and an eighth end, the seventh end being coupled to the second input terminal through the seventh switch and coupled to the decoder through the tenth switch, and the eighth end being coupled to the comparator and coupled to the reference voltage through the eighth switch.

2. The comparator-based SC circuit of claim 1 , wherein the ADC comprises N comparator(s), the ADC outputs a digital signal of N bit(s), N is a positive integer, and the decoder provides a target reference voltage to the third end of the second capacitor or the seventh end of the fourth capacitor; wherein a voltage at the first output terminal and a voltage at the second output terminal do not exceed a target range.

3. The comparator-based SC circuit of claim 2 , wherein N is seven, and the ADC comprises seven comparators.

4. The comparator-based SC circuit of claim 3 , wherein the decoder receives a first reference voltage, a second reference voltage, a third reference voltage, a fourth reference voltage, and a fifth reference voltage, the target reference voltage is one of the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, and the fifth reference voltage, and one the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, and the fifth reference voltage is substantially zero volts.

5. The comparator-based SC circuit of claim 2 , wherein N is 15, and the ADC comprises 15 comparators.

6. The comparator-based SC circuit of claim 5 , wherein the decoder receives a first reference voltage, a second reference voltage, a third reference voltage, a fourth reference voltage, a fifth reference voltage, a sixth reference voltage, and a seventh reference voltage, the target reference voltage is one of the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage, the sixth reference voltage, and the seventh reference voltage, and one of the first reference voltage, the second reference voltage, the third reference voltage, the fourth reference voltage, the fifth reference voltage, the sixth reference voltage, and the seventh reference voltage is substantially zero volts.

7. The comparator-based SC circuit of claim 2 , wherein an upper or lower limit of the target range is substantially zero volts.

8. The comparator-based SC circuit of claim 1 , wherein the SC circuit operates in a first phase or a second phase; in the first phase, the first switch, the second switch, the third switch, the sixth switch, the seventh switch, and the eighth switch are turned on, while the fourth switch, the fifth switch, the ninth switch, and the tenth switch are turned off; in the second phase, the first switch, the second switch, the third switch, the sixth switch, the seventh switch, and the eighth switch are turned off, while the fourth switch, the fifth switch, the ninth switch, and the tenth switch are turned on.

9. The comparator-based SC circuit of claim 8 further comprises:
an eleventh switch coupled between the first output terminal and a power supply voltage; and
a twelfth switch coupled between the second output terminal and a ground level.

10. The comparator-based SC circuit of claim 9 , wherein the second phase comprises a sub-phase, and the eleventh switch and the twelfth switch are turned on in the sub-phase.

Assignees

• Realtek Semiconductor Corp

Inventors

• Huang Shih-Hsiung
• Hong Wei-Cian

Classifications

• H03H19/004

  Switched capacitor networks · CPC title

• H03M1/361

  having a separate comparator and reference value for each quantisation level, i.e. full flash converter type · CPC title

• H03M1/466 Primary

  using switched capacitors · CPC title

• H03M1/167 Primary

  all stages comprising simultaneous converters (H03M1/165 takes precedence) · CPC title