Semiconductor component with a stress compensation layer and a method for manufacturing a semiconductor component

Patent metadata

Field	Value
Publication number	US-12206044-B2
Application number	US-201917264320-A
Country	US
Kind code	B2
Filing date	Jul 31, 2019
Priority date	Aug 2, 2018
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

A semiconductor device may include a conductive layer over a semiconductor body and a first stress compensation layer adjacent to the conductive layer. The stress compensation layer may include a defined first stress.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a metal layer over a semiconductor body,
a first stress compensation layer which has a defined first stress,
a second stress compensation layer which has a defined second stress,
the first stress compensation layer being directly adjacent to the metal layer, the second stress compensation layer being arranged on a side of the first stress compensation layer that faces away from the metal layer, wherein the first stress compensation layer has the same kind of stress as the metal layer, and
a first stress-relieving layer between the first and the second stress compensation layers, in which an absolute value of stress of the first stress-relieving layer is less than the absolute value of the first stress and less than the absolute value of the second stress.

2. The semiconductor device according to claim 1 , wherein the first stress compensation layer contains silicon oxide.

3. The semiconductor device according to claim 1 , wherein the first stress is a compressive stress.

4. The semiconductor device according to claim 1 , further comprising a third stress compensation layer having a defined third stress, which is arranged on a side of the second stress compensation layer that faces away from the metal layer.

5. The semiconductor device according to claim 1 , wherein the first stress is a tensile stress.

6. The semiconductor device according to claim 5 , wherein the second stress is a compressive stress.

7. The semiconductor device according to claim 5 , wherein the second stress is a tensile stress.

8. The semiconductor device according to claim 4 , wherein the third stress is a compressive stress.

9. The semiconductor device according to claim 1 , further comprising a third stress compensation layer having a defined third stress, which is arranged on a side of the second stress compensation layer that faces away from the metal layer, and a second stress-relieving layer between the second and third stress compensation layers, in which an absolute value of the stress of the second stress-relieving layer is less than the predetermined limit value.

10. An optoelectronic semiconductor device, comprising:
a semiconductor body comprising a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type,
a conductive layer over the semiconductor body, the conductive layer being electrically connected to the first or second semiconductor layer,
an insulating layer directly adjacent to the conductive layer,
a first stress compensation layer directly adjacent to the insulating layer, which has a defined first stress;
a second stress compensation layer having a defined second stress, which is arranged on a side of the first stress compensation layer that faces away from the conductive layer, wherein the first and second stress compensation layers are part of a passivation layer stack,
a first stress-relieving layer between the first and the second stress compensation layers, in which an absolute value of stress of the first stress-relieving layer is less than the absolute value of the first stress and less than the absolute value of the second stress.

11. The semiconductor device according to claim 10 , wherein the first stress is adapted to a stress in a layer lying between the first stress compensation layer and the semiconductor body.

12. The semiconductor device according to claim 10 , wherein the first stress is a compressive stress.

Assignees

• Osram Oled Gmbh

Inventors

• Steiner André
• Rafael Christine
• Altieri-Weimar Paola

Classifications

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H01S2301/176

  Specific passivation layers on surfaces other than the emission facet · CPC title

• H01S5/3201

  incorporating bulkstrain effects, e.g. strain compensation, strain related to polarisation · CPC title

• H01S5/2214

  based on oxides or nitrides · CPC title

• H01S5/222

  having a refractive index lower than that of the cladding layers or outer guiding layers · CPC title