Read data strobe path having variation compensation and delay lines

Patent metadata

Field	Value
Publication number	US-12205673-B1
Application number	US-202217945902-A
Country	US
Kind code	B1
Filing date	Sep 15, 2022
Priority date	Sep 15, 2022
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.

First claim

What is claimed is:

1. A circuit comprising:
a set of data paths operatively coupled to a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device and configured to provide data signals that carry data bits read from the DDR DRAM memory device; and
a read data strobe (RDQS) path operatively coupled to the DDR DRAM memory device and configured to provide data strobe signals for sampling the data bits from the data signals provided by the set of data paths, the RDQS path comprising a plurality of delay line components configured to adjust the RDQS signal at a center of the data bits carried by the data signals, the plurality of delay line components comprising:
a first digital delay line component operatively coupled to an output of the DDR DRAM memory device that provides a RDQS signal, the first digital delay line component being configured to provide skew between the data signals and the RDQS signal;
a plurality of second digital delay line components operatively coupled to an output of the first digital delay line component, an individual second digital delay line component of the plurality of second digital delay line components being configured to provide de-skewing between an output signal provided by the first digital delay line component and a data signal provided by an individual data path in the set of data paths that corresponds to the individual second digital delay line component;
a plurality of third digital delay line components operatively coupled to outputs of the plurality of second digital delay line components, an individual third digital delay line component of the plurality of third digital delay line components being configured to output a rising-edge RDQS signal for sampling data bits from the data signal provided by the individual data path; and
a plurality of fourth digital delay line components operatively coupled to the outputs of the plurality of second digital delay line components, an individual fourth digital delay line component of the plurality of fourth digital delay line components being configured to output a falling-edge RDQS signal for sampling data bits from the data signal provided by the individual data path, the individual third digital delay line component and the individual fourth digital delay line component create offset between the rising-edge RDQS signal and the falling-edge RDQS signal to compensate for duty cycle distortion by creating offset.

2. The circuit of claim 1 , wherein:
the first digital delay line component is configured to generate a first delayed data strobe signal based on a first data strobe signal and a first digital delay line code of the first digital delay line component, the first digital delay line code, the first data strobe signal being generated based on the RDQS signal received by the RDQS path from the DDR DRAM memory device;
the individual second digital delay line component of the plurality of second digital delay line components is configured to a second delayed data strobe signal based on a second data strobe signal and an second digital delay line code of the individual second digital delay line component, the second data strobe signal being generated based on the first delayed data strobe signal;
the individual third digital delay line component is configured to generate a third delayed data strobe signal based on a third data strobe signal and a third digital delay line code of the individual third digital delay line component, the third data strobe signal being generated based on at least one of the second delayed data strobe signals generated by the plurality of second digital delay line components, the rising-edge RDQS signal comprising the third delayed data strobe signal; and
the individual fourth digital delay line component is configured to generate a fourth delayed data strobe signal based on a fourth data strobe signal and a fourth digital delay line code of the individual fourth digital delay line component, the fourth data strobe signal being generated based on at least one of the second delayed data strobe signals generated by the plurality of second digital delay line components, the falling-edge RDQS signal comprising the fourth delayed data strobe signal.

3. The circuit of claim 2 , comprising:
a first master delay loop sub-circuit comprising:
a fifth digital delay line component configured to generate a first delayed clock signal based on a clock signal and a fifth digital delay line code of the fifth digital delay line component; and
a first phase detector operatively coupled to an output of the fifth digital delay line component, the first phase detector being configured to determine a first phase difference between the clock signal and the first delayed clock signal, the fifth digital delay loop sub-circuit being configured to apply a first code update to the fifth digital delay line code based on the first phase difference;

a second master delay loop sub-circuit comprising:
a sixth digital delay line component configured to generate a second delayed clock signal based on the clock signal and a sixth digital delay line code of the sixth digital delay line component;
a network of components configured to model one or more logic blocks and logic gates of the RDQS path that are not included by the individual data path of the set of data paths, the network of components operatively coupled to an output of the sixth digital delay line component, the network of components being configured to generate a third delayed clock signal based on the second delayed clock signal; and
a second phase detector operatively coupled to an output of the network of components, the second phase detector being configured to determine a second phase difference between the clock signal and the third delayed clock signal, the second master delay loop sub-circuit being configured to apply a second code update to the sixth digital delay line code based on the second phase difference; and

a microcontroller configured to determine code updates for the first digital delay line code, second digital delay line codes of the plurality of second digital delay line components, third digital delay line codes of the plurality of third digital delay line components, and fourth digital delay line codes of the plurality of fourth digital delay line components based on the fifth digital delay line code and the sixth digital delay line code.

4. The circuit of claim 3 , wherein the determining of the code updates comprises:
determining, based on the first code update, a first set of code updates for the second digital delay line codes of the plurality of second digital delay line components, for the third digital delay line codes of the plurality of third digital delay line components, and for the fourth digital delay line codes of the plurality of fourth digital delay line components; and
determining, based on the first code update and the second code update, a third code update to the first digital delay line code.

5. The circuit of claim 3 , wherein the microcontroller is configured to:
perform an initial training process on digital delay line components of the RDQS path prior to the determining of the code updates based on the fifth digital delay line code and the sixth digital delay line code.

6. The circuit of claim 2 , comprising:
a first master delay loop sub-circuit comprising:
a fifth digital delay line component configured to generate a first delayed clock signal based on a clock signal and a fifth digital delay line code of the fifth digital delay line component; and
a first phase detector operatively coupled to an output of the fifth digital delay line component, the first phase detector being configured to determine a first phase difference between the clock signal and the first delayed clock sig

Assignees

• Cadence Design Systems Inc

Inventors

• Ravi Hari Anand
• Gugwad Sachin Ramesh
• Yadav Jitendra Kumar
• Wilson Thomas Evan
• Kumar Vinod

Classifications

• G11C7/1066

  Output synchronization · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C8/18 Primary

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G06F13/20

  for access to input/output bus · CPC title