Memory buffer with data scrambling and error correction

Patent metadata

Field	Value
Publication number	US-12205669-B2
Application number	US-202318513473-A
Country	US
Kind code	B2
Filing date	Nov 17, 2023
Priority date	Apr 11, 2011
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

First claim

The invention claimed is:

1. A memory controller integrated circuit comprising:
a circuit to generate respective address signals and a shared channel select signal; and
a memory interface to send the respective address signals and the shared channel select signal to a first buffer circuit of a first Dual Inline Memory Module (DIMM) and to a second buffer circuit of a second DIMM, wherein a plurality of ranks are mapped across the first DIMM and the second DIMM, each rank comprising at least one of a first plurality of memory devices of the first DIMM and at least one of a second plurality of memory devices of the second DIMM, and wherein the shared channel select signal is to initiate a rank decode function in the first buffer circuit and the second buffer circuit.

2. The memory controller integrated circuit of claim 1 , wherein the memory interface comprises a plurality of communication pins to couple the memory controller integrated circuit to a command/address bus.

3. The memory controller integrated circuit of claim 2 , wherein the plurality of communication pins comprises a plurality of address signal pins and a single channel select pin.

4. The memory controller integrated circuit of claim 3 , wherein the plurality of address signal pins is greater than or equal one half of the plurality of ranks.

5. The memory controller integrated circuit of claim 1 , wherein the memory interface comprises a plurality of data pins to couple the memory controller integrated circuit to a data bus, the data bus comprising a plurality of byte lanes to convey data being written to or read from the first DIMM and the second DIMM.

6. The memory controller integrated circuit of claim 5 , wherein a first byte lane of the plurality of byte lanes is coupled to the first DIMM and to the second DIMM, and wherein a second byte lane of the plurality of byte lanes is coupled to the first DIMM but not to the second DIMM.

7. The memory controller integrated circuit of claim 1 , wherein the first plurality of memory devices and the second plurality of memory devices comprise Dynamic Random Access Memory (DRAM) devices.

8. A method of operation of a memory controller integrated circuit comprising:
generating, by a circuit of the memory controller integrated circuit, respective address signals and a shared channel select signal; and
sending, by a memory interface of the memory controller integrated circuit, the respective address signals and the shared channel select signal to a first buffer circuit of a first Dual Inline Memory Module (DIMM) and to a second buffer circuit of a second DIMM, wherein a plurality of ranks are mapped across the first DIMM and the second DIMM, each rank comprising at least one of a first plurality of memory devices of the first DIMM and at least one of a second plurality of memory devices of the second DIMM, and wherein the shared channel select signal is to initiate a rank decode function in the first buffer circuit and the second buffer circuit.

9. The method of claim 8 , wherein the memory interface comprises a plurality of communication pins to couple the memory controller integrated circuit to a command/address bus.

10. The method of claim 9 , wherein the plurality of communication pins comprises a plurality of address signal pins and a single channel select pin.

11. The method of claim 10 , wherein the plurality of address signal pins is greater than or equal one half of the plurality of ranks.

12. The method of claim 8 , wherein the memory interface comprises a plurality of data pins to couple the memory controller integrated circuit to a data bus, the data bus comprising a plurality of byte lanes to convey data being written to or read from the first DIMM and the second DIMM.

13. The method of claim 12 , wherein a first byte lane of the plurality of byte lanes is coupled to the first DIMM and to the second DIMM, and wherein a second byte lane of the plurality of byte lanes is coupled to the first DIMM but not to the second DIMM.

14. The method of claim 8 , wherein the first plurality of memory devices and the second plurality of memory devices comprise Dynamic Random Access Memory (DRAM) devices.

15. An apparatus comprising:
a circuit to generate respective address signals and a shared channel select signal; and
a memory interface to send the respective address signals and the shared channel select signal to a first buffer circuit of a first memory module and to a second buffer circuit of a second memory module, wherein a plurality of ranks are mapped across the first memory module and the second memory module, each rank comprising at least one of a first plurality of memory devices of the first memory module and at least one of a second plurality of memory devices of the second memory module, and wherein the shared channel select signal is to initiate a rank decode function in the first buffer circuit and the second buffer circuit.

16. The apparatus of claim 15 , wherein the memory interface comprises a plurality of communication pins to couple the apparatus to a command/address bus.

17. The apparatus of claim 16 , wherein the plurality of communication pins comprises a plurality of address signal pins and a single channel select pin.

18. The apparatus of claim 17 , wherein the plurality of address signal pins is greater than or equal one half of the plurality of ranks.

19. The apparatus of claim 15 , wherein the memory interface comprises a plurality of data pins to couple the apparatus to a data bus, the data bus comprising a plurality of byte lanes to convey data being written to or read from the first memory module and the second memory module.

20. The apparatus of claim 19 , wherein a first byte lane of the plurality of byte lanes is coupled to the first memory module and to the second memory module, and wherein a second byte lane of the plurality of byte lanes is coupled to the first memory module but not to the second memory module.

Assignees

• Rambus Inc

Inventors

• Haywood Christopher
• Wang David

Classifications

• G06F11/1044

  with specific ECC/EDC distribution · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title