Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12205506-B2
Application number	US-202117781988-A
Country	US
Kind code	B2
Filing date	Mar 24, 2021
Priority date	Mar 24, 2021
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

A display substrate and a display device are provided. The display substrate includes a shift register unit, a first clock signal line and a first power line, the shift register unit includes a charge pump circuit, and the charge pump circuit includes a first capacitor, a first transistor and a second capacitor. The charge pump circuit is electrically connected with a first input node and a first node, respectively. A first electrode plate of the first capacitor is connected with the first clock signal line, a second electrode plate of the first capacitor is connected with the first input node, a first electrode plate of the second capacitor is connected with the first power line, a second electrode plate of the second capacitor is connected with the first node, a gate electrode of the first transistor is connected with a first electrode or a second electrode of the first transistor.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate, and
a shift register unit, a first clock signal line, and a first power line which are all provided in a peripheral region of the base substrate, wherein the shift register unit comprises a charge pump circuit,
the first clock signal line is configured to supply a first clock signal to the shift register unit,
the first power line is configured to supply a first power voltage to the shift register unit,
the charge pump circuit comprises a first capacitor and a first transistor, and the charge pump circuit is electrically connected with a first input node and a first node,
a first electrode plate of the first capacitor is connected with the first clock signal line, a second electrode plate of the first capacitor is connected with the first input node,
a gate electrode of the first transistor is connected with a first electrode or a second electrode of the first transistor,
and an orthogonal projection of the first capacitor on the base substrate is adjacent to an orthogonal projection of the first transistor on the base substrate,
wherein the display substrate further comprises a first connection electrode and a second connection electrode, wherein
the gate electrode of the first transistor is connected with the first electrode of the first transistor through the first connection electrode to form a diode structure, a first end of the first connection electrode is connected with the first electrode of the first transistor, a second end of the first connection electrode is connected with gate electrode of the first transistor, a first end of the second connection electrode is connected with the second electrode of the first transistor, the first electrode of the first transistor is connected with an active layer of the first transistor through a first via hole, and an orthogonal projection of a channel of the first transistor on the base substrate does not overlap with an orthogonal projection of the first via hole on the base substrate, wherein the first connection electrode is connected with the gate electrode of the first transistor through a second via hole, and the orthogonal projection of the channel of the first transistor on the base substrate does not overlap with an orthogonal projection of the second via hole on the base substrate.

2. The display substrate according to claim 1 , wherein the charge pump circuit is configured to, under control of the first clock signal supplied by the first clock signal line during a first period, convert a potential of the first input node from a first voltage signal to a second voltage signal, and transmit the second voltage signal to the first node, and is configured to maintain a potential of the first node during a second period.

3. The display substrate according to claim 1 , wherein a height of the second via hole in a direction perpendicular to the base substrate is smaller than a height of the first via hole in the direction perpendicular to the base substrate, the first via hole penetrates a first insulating layer, a second insulating layer, and a third insulating layer, and the second via hole penetrates the second insulating layer and the third insulating layer.

4. The display substrate according to claim 1 , wherein the first capacitor is a structure of three capacitors connected in parallel, and the structure of the three capacitors connected in parallel comprises a first portion of the second electrode plate, a second portion of the second electrode plate, a first portion of the first electrode plate, and a second portion of the first electrode plate.

5. The display substrate according to claim 1 , wherein an orthogonal projection of the second electrode plate of the first capacitor on the base substrate partially overlaps with an orthogonal projection of the first electrode of the first transistor on the base substrate.

6. The display substrate according to claim 1 , further comprising a first conductive line and a third connection electrode, wherein a first end of the first conductive line is connected with the first clock signal line, a second end of the first conductive line is connected with a first end of the third connection electrode, and a second end of the third connection electrode is connected with the first electrode plate of the first capacitor.

7. The display substrate according to claim 6 , further comprising a fourth connection electrode and a fifth connection electrode, wherein the charge pump circuit further comprises a second transistor, a first end of the fourth connection electrode is connected with a gate electrode of the second transistor, the first end of the fourth connection electrode is connected with the second electrode plate of the first capacitor, a first end of the fifth connection electrode is connected with a first electrode of the second transistor, a second end of the fifth connection electrode is connected with the first conductive line, the first conductive line is connected with the first clock signal line, and a second electrode of the second transistor is connected with the third connection electrode.

8. The display substrate according to claim 1 , wherein the first clock signal line extends along a first direction on the base substrate, the first capacitor and the first transistor are sequentially arranged in a second direction, and the first direction intersects with the second direction.

9. The display substrate according to claim 8 , further comprising a sixth connection electrode, a seventh connection electrode, an eighth connection electrode, a ninth connection electrode, a tenth connection electrode, an eleventh connection electrode, a second clock signal line and a second power line, wherein
the second clock signal line is configured to supply a second clock signal to the shift register unit, the second power line is configured to supply a second power voltage to the shift register unit, and the shift register unit further comprises a first node control transistor, a first output transistor, a second output transistor, and a third capacitor;
a first electrode of the first output transistor is electrically connected with the first power line through the seventh connection electrode, and a second electrode of the first output transistor is electrically connected with a driving signal output terminal through the eighth connection electrode;
a gate electrode of the second output transistor is electrically connected with a first electrode plate of the third capacitor through the ninth connection electrode, a first electrode of the second output transistor is electrically connected with the driving signal output terminal through the eighth connection electrode, and a second electrode of the second output transistor is electrically connected with the second clock signal line through the tenth connection electrode;
a second electrode plate of the third capacitor is electrically connected with the second clock signal line;
a first electrode of the first node control transistor is electrically connected with the second power line through the sixth connection electrode, and a second electrode of the first node control transistor is electrically connected with the first node through the eleventh connection electrode; and
an orthogonal projection of the third capacitor on the base substrate is adjacent to an orthogonal projection of the second output transistor on the base substrate.

10. The display substrate according to claim 9 , wherein the second power line and the first power line are separately provided on both sides of the shift register unit; and
the second clock signal line and the second power line are located on the same side of the shift r

Assignees

• Boe Technology Group Co Ltd

Inventors

• Lu Jiangnan
• Shang Guangliang
• Liu Libin
• Han Long
• Feng Yu

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2320/0209

  Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title