Near-memory compute module

Patent metadata

Field	Value
Publication number	US-12204758-B2
Application number	US-202318235068-A
Country	US
Kind code	B2
Filing date	Aug 17, 2023
Priority date	Jan 7, 2014
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.

First claim

What is claimed is:

1. A memory module comprising:
a plurality of dynamic random access memory (DRAM) devices; and
a transactional memory controller device comprising a first interface to couple to a host device, a second interface coupled to the plurality of DRAM devices, wherein the transactional memory controller device is to:
decode a first command in a first portion of first signals received from the host device;
perform, in response to the first command, a set of data transformation operations on a dataset stored in at least one DRAM device of the plurality of DRAM devices based on data received from the host device, wherein the set of data transformation operations is performed by the transactional memory controller device without interaction with the host device;
send results of the set of data transformation operations to the host device via the first interface;
decode a second command in a second portion of the first signals to perform an access operation, wherein the access operation is a write access operation or a read access operation; and
perform, in response to the second command, the access operation with the plurality of DRAM devices via the second interface.

2. The memory module of claim 1 , wherein the transactional memory controller device comprises a transaction processor and at least one memory controller, wherein the transaction processor is to receive the first command and the second command from a first memory controller of the host device over a system bus based on an instruction from a central processing unit (CPU) of the host device.

3. The memory module of claim 1 , wherein the transactional memory controller device comprises a transaction processor and at least one memory controller, wherein the transaction processor is to forward the second command to the at least one memory controller in response to the second command, wherein the at least one memory controller is to initiate execution of the access operation with the plurality of DRAM device via the second interface in response to the second command.

4. The memory module of claim 1 , wherein the transactional memory controller device comprises a transaction processor, at least one memory controller, and an off-load engine coupled to the transaction processor, wherein the off-load engine is to accelerate the set of data transformation operations by performing one or more data transformation operations of the set of data transformations.

5. The memory module of claim 1 , wherein the one or more data transformation operations are at least a compress operation, a uncompress operation, an encryption operation, a decryption operation, a Galois field arithmetic operation, a hashing operation, or an indexing operation.

6. The memory module of claim 1 , wherein the transactional memory controller device comprises a transaction processor, at least one memory controller, and an off-load engine coupled to the transaction processor, wherein the transaction processor and the off-load engine perform the set of data transformation operations as parallel background processing.

7. The memory module of claim 1 , wherein the DRAM devices are operable according to a JEDEC standard.

8. The memory module of claim 1 , wherein the transactional memory controller device comprises a set of data buffers to send and receive the first signals to and from the host device and send and receive second signals to and from the plurality of DRAM devices, wherein the set of data buffers allow the plurality of DRAM devices to emulate a type of Dual In-Line Memory Module (DIMM) selected from an un-buffered DIMM type (UDIMM), a load-reduction DIMM type (LRDIMM), and a registered DIMM type (RDIMM).

9. The memory module of claim 1 , wherein the transactional memory controller device comprises a transaction processor and at least one memory controller, wherein the transaction processor is to communicate with a first memory controller of the host device using the first interface so as to appear as physical memory to the first memory controller.

10. The memory module of claim 1 , wherein the transactional memory controller device comprises a transaction processor and at least one memory controller, wherein the transaction processor and the at least one memory controller reside within an integrated circuit package periphery.

11. The memory module of claim 10 , wherein the transaction processor comprises:
data plane memory;
control plane memory; and
data buffers coupled to the first interface.

12. The memory module of claim 1 , wherein the transactional memory controller device comprises:
a plurality of processor cores;
a plurality of off-load engines;
at least one memory controller; and
a non-volatile memory controller, wherein the plurality of processor cores, the plurality of off-load engines, the at least one memory controller, and the non-volatile memory controller reside within an integrated circuit package periphery.

13. The memory module of claim 12 , further comprising a non-volatile memory device coupled to the non-volatile memory controller, wherein the non-volatile memory controller resides within the integrated circuit package periphery.

14. The memory module of claim 1 , wherein the transactional memory controller device comprises a transaction processor and at least one memory controller, wherein the transaction processor, the at least one memory controller, and the plurality of DRAM devices reside within an integrated circuit package periphery.

15. The memory module of claim 1 , wherein the transactional memory controller device comprises a transaction processor and at least one memory controller, wherein the transaction processor is further to:
intercept the first portion of the first signals;
determine, based on the first command, a set of one or more instructions to perform the set of data transformation operations;
execute the set of one or more instructions during one or more wait times after the first portion is intercepted and before the results from the set of data transformation operations are expected by a first memory controller of the host device; and
determine the results from execution of the set of one or more instructions.

16. The memory module of claim 15 , wherein the transaction processor is further to:
intercept the second portion of the first signals, wherein the access operation is decoded in the second portion of the first signals;
forward the second portion of the first signals to the at least one memory controller to initiate execution of the access operation as the write access operation or the read access operation; and
when the second portion corresponds to the write access operation, receive write data associated with the write access operation from the first memory controller and forward the write data to the at least one memory controller; and
when the second portion corresponds to the read access operation, receive read data associated with the read access operation from the at least one memory controller and forward, to the first memory controller, the read data during one or more wait times after the first portion of the first signals is intercepted and before the results of the set of data transformation operations are expected by the first memory controller.

17. A compute dual in-line memory module (DIMM) comprising:
a plurality of dynamic random access memory (DRAM) devices;
a transaction processor coupled to a first interface to send and receive first signals to and from a first memory controller of a host device; and
a second memory controller coupled to the tra

Assignees

• Rambus Inc

Inventors

• Wang David
• Saxena Nirmal

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F13/00

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• G06F13/1642 Primary

  with request queuing · CPC title