Integrated circuitry comprising a memory array comprising strings of memory cells and method used in forming a memory array comprising strings of memory cells

Patent metadata

Field	Value
Publication number	US-12200929-B2
Application number	US-202117408813-A
Country	US
Kind code	B2
Filing date	Aug 23, 2021
Priority date	Aug 23, 2021
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another. The lower portion comprises a horizontal line above the conductor tier that runs parallel with the laterally-spaced memory blocks in the first vertical stack. Other embodiments, including method, are disclosed.

First claim

The invention claimed is:

1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a lower portion of a stack that will comprise vertically-alternating different-composition first tiers and second tiers, the stack comprising laterally-spaced memory-block regions, the lower portion comprising horizontally-elongated lines that are individually between immediately-laterally-adjacent of the memory-block regions, individual of the lines comprising sacrificial material, the individual lines comprising laterally-opposing uppermost corner regions that are exposed above laterally-opposing sidewalls there-below, the laterally-opposing sidewalls below the corner regions being covered by lower-portion material;
removing the sacrificial material from the exposed corner regions in a greater amount diagonally in a vertical plane than orthogonally relative to exposed sidewalls of the corner regions and than orthogonally relative to exposed tops of the corner regions;
after the removing of the sacrificial material from the exposed corner regions, forming the vertically-alternating different-composition first tiers and second tiers of an upper portion of the stack above the lower portion and the lines, and forming channel-material strings that extend through the first tiers and the second tiers in the upper portion to the lower portion;
forming horizontally-elongated trenches through the upper portion and that are individually between the immediately-laterally-adjacent memory-block regions and that extend to the individual line there-between in the lower portion;
removing the sacrificial material of the lines through the trenches; and
forming intervening material in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines.

2. The method of claim 1 wherein the removing of the sacrificial material from the exposed corner regions comprises etching.

3. The method of claim 2 wherein the etching is isotropic.

4. The method of claim 1 wherein the lower portion at least as initially formed comprises multiple of the first tiers and multiple of the second tiers.

5. The method of claim 1 wherein individual of the trenches where joining with its individual line there-below are narrower than an uppermost surface of its individual line there-below at least prior to the removing of the sacrificial material from the exposed corner regions.

6. The method of claim 1 wherein:
prior to the removing of the sacrificial material from the exposed corner regions, the lines and the lower-portion material comprise respective uppermost surfaces that are individually planar and are collectively co-planar; and
prior to the removing of the sacrificial material from the exposed corner regions, the exposed corner regions are so exposed by removing the lower-portion material to have its uppermost surfaces be lower than the uppermost surfaces of the lines.

7. The method of claim 6 wherein the removing the lower-portion material to have its uppermost surfaces be lower than the uppermost surfaces of the lines comprises etching.

8. The method of claim 6 sequentially comprising:
after the removing of the sacrificial material from the exposed corner regions, forming more material over the uppermost surfaces of the lines and aside the lines to a greater thickness than thickness of the lower-portion material that was removed to have its uppermost surfaces be higher than the uppermost surfaces of the lines; and
planarizing the more material back at least to the uppermost surfaces of the lines such that the lines and the more material comprise respective uppermost surfaces that are individually planar and are collectively co-planar.

9. The method of claim 1 wherein,
the stack comprises a first vertical stack that is formed above a conductor tier comprising conductor material; and
the stack comprises a second vertical stack aside the first vertical stack, the second vertical stack being above the conductor tier and comprising an upper portion and a lower portion, the upper portion of the second vertical stack comprising vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another, the lower portion in the second vertical stack comprising a horizontal line above the conductor tier that runs parallel with the laterally-spaced memory blocks in the first vertical stack.

10. The method of claim 9 wherein the horizontal line in the second vertical stack extends upwardly into the upper portion.

11. The method of claim 10 wherein the horizontal line in the second vertical stack comprises a vertical wall in the upper and lower portions, the vertical wall extending through at least a majority of the first and second insulating tiers in the upper portion.

12. The method of claim 11 wherein that portion of the vertical wall in the upper portion where joining with that portion of the vertical wall in the lower portion being narrower than an uppermost part of that portion of the vertical wall in the lower portion.

13. The method of claim 9 wherein the horizontal line in the second vertical stack does not extend upwardly into the upper portion.

14. The method of claim 13 wherein the horizontal line in the second vertical stack has uppermost laterally-opposing uppermost corner regions in the lower portion that individually have a curved outermost surface.

15. The method of claim 9 wherein the horizontal line in the second vertical stack is conductive and dummy.

16. The method of claim 9 wherein the horizontal line in the second vertical stack is insulative.

17. The method of claim 1 wherein,
the stack comprises a first vertical stack; and
the stack comprises a second vertical stack aside the first vertical stack, the second vertical stack an upper portion and a lower portion, the upper portion of the second vertical stack comprising vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another, the lower portion in the second vertical stack comprising a horizontal dummy conductive line that runs parallel with the laterally-spaced memory blocks in the first vertical stack.

18. The method of claim 17 wherein the horizontal line in the second vertical stack has uppermost laterally-opposing uppermost corner regions in the lower portion that individually have a curved outermost surface.

19. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
stack that will comprise forming a lower portion of a vertically-alternating different-composition first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, the lower portion comprising horizontally-elongated lines that are individually between immediately-laterally-adjacent of the memory-block regions, individual of the lines comprising sacrificial material, the individual lines comprising laterally-opposing uppermost corner regions that are exposed above laterally-opposing sidewalls there-below, the laterally-opposing sidewalls below the corner regions being covered by a lower-portion material;
removing the sacrificial material from the exposed corner regions in a greater amount diagonally in a vertical plane than orthogonally relative to exposed sidewalls of the corner regions and than orthogonally relative to exposed tops of the corner regions;
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Assignees

• Micron Technology Inc

Inventors

• Howder Collin
• Barclay M Jared
• Bhartia Bhavesh
• Carter Chet E
• Hopkins John D
• Li Andrew
• Li Haoyu
• Scarbrough Alyssa N
• Waldo Grady S

Classifications

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title