Parallel-to-serial conversion circuit, parallel-to-serial conversion circuit layout, and memory

Patent metadata

Field	Value
Publication number	US-12199645-B2
Application number	US-202217849942-A
Country	US
Kind code	B2
Filing date	Jun 27, 2022
Priority date	Jan 10, 2022
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where first input end is configured to receive high level signal, second input end is configured to receive low level signal, control ends are connected to selection unit and output end is connected to serial wire, and selection unit is configured to receive selection signal and at least two branch signals and configured to select, based on selection signal, one branch signal and transmit it to parallel branch; serial wire configured to organize signals output by parallel branches into serial signal; and drive units connected in parallel with each other and connected to serial wire for enhancing drive capability of serial wire, output ends of drive units being connected with each other and configured to output serial signal, and each drive unit being disposed adjacent to a respective parallel branch.

First claim

The invention claimed is:

1. A parallel-to-serial conversion circuit, comprising:
a plurality of parallel branches, each comprising a first input end, a second input end, control ends and an output end,
wherein the first input end is configured to receive a high level signal, the second input end is configured to receive a low level signal, the control ends are connected to a selection unit, and the output end is connected to a serial wire, and
the selection unit is configured to receive a selection signal and at least two branch signals, and configured to select, based on the selection signal, one of the branch signals and transmit a selected branch signal to the parallel branch;
the serial wire, configured to organize signals output by the plurality of parallel branches into a serial signal; and
a plurality of drive units, connected in parallel with each other and then connected to the serial wire, for enhancing drive capability of the serial wire, wherein output ends of the plurality of drive units are connected with each other and configured to output the serial signal,
wherein each of the drive units is disposed adjacent to a respective one of the parallel branches.

2. The parallel-to-serial conversion circuit of claim 1 , wherein a number of the drive units is equal to a number of the parallel branches.

3. The parallel-to-serial conversion circuit of claim 1 , wherein the selection unit comprises a multiplexer and a selection sub-unit,
wherein the multiplexer is configured to receive the at least two branch signals, and be connected to the selection sub-unit;
the selection sub-unit is configured to receive a selection command and generate the selection signal based on the selection command; and
the multiplexer is configured to select, based on the selection signal, one of the branch signals and transmit the selected branch signal to the parallel branch through the control end.

4. The parallel-to-serial conversion circuit of claim 3 , wherein the multiplexer only receives two of the branch signals, and the selection command is an internal clock signal.

5. The parallel-to-serial conversion circuit of claim 4 , wherein a period of the selection signal is n times of a period of the internal clock signal, and n is a branch number of the plurality of parallel branches.

6. The parallel-to-serial conversion circuit of claim 4 , wherein at most one of the selection signal and the branch signal received by a same selection unit is a continuous signal.

7. The parallel-to-serial conversion circuit of claim 4 , wherein in the selection signals received by the selection units connected to the plurality of parallel branches, high levels are alternately distributed.

8. The parallel-to-serial conversion circuit of claim 4 , wherein in the selection signals received by the selection units connected to the plurality of parallel branches, high levels have an overlapped part.

9. The parallel-to-serial conversion circuit of claim 1 , wherein each parallel branch comprises a switch Positive-channel Metal-Oxide-Semiconductor (PMOS) transistor and a switch Negative-channel Metal-Oxide-Semiconductor (NMOS) transistor,
wherein a gate of the switch PMOS transistor and a gate of the switch NMOS transistor are used as the control ends of the parallel branch for connecting the selection unit;
a source of the switch PMOS transistor and a drain of the switch NMOS transistor are connected to the serial wire;
a drain of the switch PMOS transistor is used as the first input end of the parallel branch for receiving the high level signal; and
a source of the switch NMOS transistor is used as the second input end of the parallel branch for receiving the low level signal.

10. The parallel-to-serial conversion circuit of claim 1 , wherein each drive unit comprises two inverters, wherein an input end of one of the inverters is connected to the serial wire, and an output end of the inverter is connected to an input end of the other inverter; and an output end of the other inverter is configured to output the serial signal.

11. The parallel-to-serial conversion circuit of claim 10 , wherein the inverter comprises a drive PMOS transistor and a drive NMOS transistor,
wherein a gate of the drive PMOS transistor is connected to a gate of the drive NMOS transistor, and a source of the drive PMOS transistor is connected to a drain of the drive NMOS transistor; and
a drain of the drive PMOS transistor is configured to receive the high level signal, and a source of the drive NMOS transistor is configured to receive the low level signal.

12. A parallel-to-serial conversion circuit layout, configured to form the parallel-to-serial conversion circuit of claim 1 , the parallel-to-serial conversion circuit layout comprising
parallel branch layouts, each configured to form the parallel branch, and form the selection unit connected to the parallel branch; and
drive unit layouts, each configured to form the drive unit,
wherein adjacently disposed parallel branch layout and drive unit layout are disposed in a same layout layer; projections of the parallel branch layouts in a direction perpendicular to the layout layer are overlapped; and projections of the drive unit layouts in the direction perpendicular to the layout layer are overlapped; and
projections of serial wires for connecting the parallel branch layouts and the respective drive unit layouts in the direction perpendicular to the layout layer are overlapped.

13. The parallel-to-serial conversion circuit layout of claim 12 , wherein a number of the drive unit layouts is equal to a number of the parallel branch layouts.

14. A memory using the parallel-to-serial conversion circuit layout of claim 12 in a layout framework of the memory.

15. A memory having a parallel-to-serial conversion circuit, wherein the parallel-to-serial conversion circuit comprises:
a plurality of parallel branches, each comprising a first input end, a second input end, control ends and an output end,
wherein the first input end is configured to receive a high level signal, the second input end is configured to receive a low level signal, the control ends are connected to a selection unit, and the output end is connected to a serial wire, and
the selection unit is configured to receive a selection signal and at least two branch signals, and configured to select, based on the selection signal, one of the branch signals and transmit a selected branch signal to the parallel branch;
the serial wire, configured to organize signals output by the plurality of parallel branches into a serial signal; and
a plurality of drive units, connected in parallel with each other and then connected to the serial wire, for enhancing drive capability of the serial wire, wherein output ends of the plurality of drive units are connected with each other and configured to output the serial signal,
wherein each of the drive units is disposed adjacent to a respective one of the parallel branches.

Assignees

• Changxin Memory Tech Inc

Inventors

• Huang Keqin
• Ji Kangling

Classifications

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C2207/107

  Serial-parallel conversion of data or prefetch · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C7/1066

  Output synchronization · CPC title

• G11C7/1093

  Input synchronization · CPC title