Semiconductor switches for high voltage operations

Patent metadata

Field	Value
Publication number	US-12199597-B2
Application number	US-202318350874-A
Country	US
Kind code	B2
Filing date	Jul 12, 2023
Priority date	Jun 23, 2022
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Semiconductor switches for high voltage operations are described. The semiconductor switch includes a first DE-NMOS FET including a gate coupled to a node of the switch with its source and drain coupled to input and output nodes, respectively. The switch also includes a second DE-NMOS FET with a drain coupled to the node. A gate of the second DE-NMOS FET is configured to receive a signal enabling or disabling the switch. The switch includes a voltage source (e.g., a voltage-controlled voltage source) coupled to the node, which supplies a first voltage at the node. The first voltage is greater than a second voltage at the input node by a predetermined amount such that the first DE-NMOS FET may operate within a safe operating area while supporting high voltage operations. The switch also includes a current source configured to supply current to the voltage source.

First claim

What is claimed is:

1. A circuit, comprising:
an n-channel metal-oxide-semiconductor field effect transistor (nMOS FET) including a gate coupled to a node of the circuit, wherein a source and a drain of the nMOS FET are coupled to an input node and an output node of the circuit, respectively; and
a voltage source coupled to the node, wherein the voltage source is configured to provide a first voltage at the node, the first voltage greater than a second voltage at the input node by a predetermined amount, and wherein the voltage source includes:
a p-channel metal-oxide semiconductor field effect transistor (pMOS FET) with a gate coupled to the input node and a drain coupled to a ground node; and
one or more diodes connected in series, wherein a source of the pMOS FET is coupled to a cathode of a first diode of the one or more diodes.

2. The circuit of claim 1 , further comprising:
a current source coupled to the node, the current source configured to supply current to the voltage source.

3. The circuit of claim 1 , wherein the predetermined amount is less than a breakdown voltage across the gate and source (BVgs) of the nMOS FET.

4. The circuit of claim 1 , wherein the predetermined amount corresponds to a voltage applied across the gate and source (Vgs) of the nMOS FET that activates the nMOS FET to transfer the second voltage to the output node.

5. The circuit of claim 1 , wherein the predetermined amount is proportional to a total of a threshold voltage of the pMOS FET and a sum of threshold voltages of the one or more diodes.

6. The circuit of claim 1 , wherein the nMOS FET is a first nMOS FET, and each diode of the one or more diodes corresponds to a second nMOS FET with a drain and a gate connected together.

7. The circuit of claim 1 , wherein the nMOS FET is a first nMOS FET, and the circuit further comprises:
a second nMOS FET with a drain coupled to the node, wherein a gate of the second nMOS FET is configured to receive a signal enabling or disabling the circuit.

8. The circuit of claim 7 , wherein the first nMOS FET transfers the second voltage at the input node to the output node in response to the signal enabling the circuit applied at the gate of the second nMOS FET.

9. The circuit of claim 7 , wherein the first nMOS FET isolates the output node from the input node in response to the signal disabling the circuit applied at the gate of the second nMOS FET.

10. A circuit, comprising:
a first component including an output node, the first component configured to generate a first voltage at the output node;
a second component coupled to a power supply node, the second component configured to operate with the first voltage; and
a first switch connected between the output node and the power supply node, wherein the first switch includes:
a first n-channel metal-oxide-semiconductor field effect transistor (nMOS FET) including a gate coupled to a first node of the first switch, wherein a source and a drain of the first nMOS FET are coupled to the output node and the power supply node, respectively; and
a first voltage source coupled to the first node, wherein the first voltage source is configured to generate a second voltage greater than the first voltage by a first predetermined amount, and wherein the first voltage source includes:
a p-channel metal-oxide-semiconductor field effect transistor (pMOS FET) with a gate coupled to the output mode and a drain coupled to a ground node; and
one or more diodes connected in series, wherein a source of the pMOS FET is coupled to a cathode of a first diode of the one or more diodes.

11. The circuit of claim 10 , wherein the first switch further comprises a first current source coupled to the first node, the first current source configured to supply first current to the first voltage source.

12. The circuit of claim 10 , wherein the first predetermined amount corresponds to a voltage applied across the gate and source (Vgs) of the first nMOS FET that activates the first nMOS FET to transfer the first voltage to the power supply node.

13. The circuit of claim 11 , wherein the first switch further comprises:
a second nMOS FET with a drain coupled to the first node, wherein a gate of the second nMOS FET is configured to receive a first signal enabling or disabling the first switch.

14. The circuit of claim 13 , wherein the first nMOS FET transfers the first voltage at the output node to the power supply node in response to the first signal enabling the first switch applied at the gate of the second nMOS FET.

15. The circuit of claim 13 , wherein the first nMOS FET isolates the output node from the power supply node in response to the first signal disabling the first switch applied at the gate of the second nMOS FET.

16. The circuit of claim 13 , further comprising a second switch connected between the power supply node and a pad connected to an external power source configured to supply a third voltage at the pad, wherein the second switch includes:
a third nMOS FET including a gate coupled to a second node of the second switch, wherein a source and a drain of the third nMOS FET are coupled to the pad and the power supply node, respectively;
a fourth nMOS FET with a drain coupled to the second node, wherein a gate of the fourth nMOS FET is configured to receive a second signal enabling or disabling the second switch; and
a second voltage source coupled to the second node, wherein the second voltage source is configured to generate a fourth voltage greater than the third voltage by a second predetermined amount.

17. The circuit of claim 16 , wherein the second switch further comprises a second current source coupled to the second node, the second current source configured to supply second current to the second voltage source.

18. The circuit of claim 16 , wherein:
when the first signal enables the first switch, the second signal disables the second switch; and
when the second signal enables the second switch, the first signal disables the first switch.

19. The circuit of claim 16 , wherein the third nMOS FET transfers the third voltage to the power supply node in response to the second signal enabling the second switch applied at the gate of the fourth nMOS FET.

20. The circuit of claim 16 , wherein the third nMOS FET isolates the pad from the power supply node in response to the second signal disabling the second switch applied at the gate of the fourth nMOS FET.

21. The circuit of claim 10 , wherein the first component includes a voltage level shifter configured to generate the first voltage based on a third voltage less than the first voltage.

22. The circuit of claim 10 , wherein the second component includes an array of electrically erasable programmable read-only memory (EEPROM) cells.

Assignees

• Texas Instruments Inc

Inventors

• Sinha Rohan
• Kulshrestha Rajat

Classifications

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H10D30/65

  Lateral DMOS [LDMOS] FETs · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title