Isolation structure for separating different transistor regions on the same semiconductor die

Patent metadata

Field	Value
Publication number	US-12199102-B2
Application number	US-202217721397-A
Country	US
Kind code	B2
Filing date	Apr 15, 2022
Priority date	Apr 15, 2022
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

First claim

What is claimed is:

1. A method of producing a semiconductor device, the method comprising:
growing an epitaxial layer or layer stack on a semiconductor substrate;
forming a plurality of transistor cells of a first type in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor;
forming a plurality of transistor cells of a second type different than the first type in a second region of the epitaxial layer or layer stack; and
forming an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack,
wherein sidewalls and a bottom of the isolation structure comprise a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack.

2. The method of claim 1 , wherein forming the isolation structure comprises:
forming oxide islands in a first epitaxial layer of the epitaxial layer or layer stack or in the semiconductor substrate;
after covering the oxide islands by epitaxial overgrowth and completing the epitaxial layer or layer stack, etching a plurality of trenches into the second region of the epitaxial layer or layer stack such that a bottom part of the trenches are laterally separated from one another by the oxide islands, wherein an outermost trench of the plurality of trenches surrounds the other trenches and laterally delimits the second region of the epitaxial layer or layer stack; and
forming an oxide layer on sidewalls and a bottom of the trenches such that the oxide layer connects the oxide islands.

3. The method of claim 2 , wherein the outermost trench is completely filled by the oxide layer.

4. The method of claim 2 , wherein a central part of the outermost trench is devoid of the oxide layer, and wherein forming the isolation structure comprises:
forming an electrode in the central part of the outermost trench, the electrode being separated from the epitaxial layer or layer stack by the oxide layer and the oxide islands.

5. The method of claim 2 , wherein forming the plurality of transistor cells of the second type in the second region of the epitaxial layer or layer stack comprises:
forming doped transistor regions in semiconductor mesas delimited by the trenches.

6. The method of claim 2 , wherein forming the plurality of transistor cells of the second type in the second region of the epitaxial layer or layer stack comprises:
forming a gate electrode in the trenches surrounded by the outermost trench.

7. The method of claim 6 , wherein forming the plurality of transistor cells of the second type in the second region of the epitaxial layer or layer stack comprises:
forming a field electrode below the gate electrode in the trenches surrounded by the outermost trench.

8. The method of claim 2 , wherein forming the plurality of transistor cells of the first type in the first region of the epitaxial layer or layer stack comprises:
etching a plurality of gate trenches into the first region of the epitaxial layer or layer stack via a common etching process by which the plurality of trenches are etched into the second region of the epitaxial layer or layer stack.

9. The method of claim 2 , further comprising:
after covering the oxide islands by the epitaxial overgrowth but before etching the plurality of trenches, planarizing the epitaxial overgrowth;
forming a mask on the planarized epitaxial overgrowth, the mask having an opening that exposes an area of the planarized epitaxial overgrowth vertically aligned with the oxide islands; and
implanting dopant atoms into the planarized epitaxial overgrowth through the opening in the mask to form a doped buried layer above the oxide islands.

10. The method of claim 1 , further comprising:
increasing a doping concentration in the second region of the epitaxial layer or layer stack, in a first area of the second region that adjoins the dielectric material at the bottom of the isolation structure.

11. The method of claim 10 , further comprising:
increasing a doping concentration in the second region of the epitaxial layer or layer stack, in a second area of the second region interposed between the first area of the second region and a contact that is recessed into the second region of the epitaxial layer or layer stack between the outermost trench and an end of the trenches surrounded by the outermost trench.

12. The method of claim 11 , further comprising:
forming a contact in the second region of the epitaxial layer or layer stack and that extends to the second area of the second region in an area between the outermost trench and an end of the trenches surrounded by the outermost trench.

13. The method of claim 1 , wherein forming the isolation structure comprises:
etching a plurality of trenches into the second region of the epitaxial layer or layer stack, wherein the trenches delimit doped semiconductor mesas in the second region of the epitaxial layer or layer stack, wherein an outermost trench of the plurality of trenches surrounds the other trenches and laterally delimits the second region of the epitaxial layer or layer stack;
extending a depth of the plurality of trenches further into the second region of the epitaxial layer or layer stack;
forming a contiguous region of oxidized semiconductor material along a bottom part of the trenches in an area where the depth of the plurality of trenches was extended; and
forming an oxide layer on sidewalls of the trenches and that connects to the contiguous region of oxidized semiconductor material.

14. The method of claim 13 , wherein the outermost trench is completely filled by the oxide layer.

15. The method of claim 13 , wherein a central part of the outermost trench is devoid of the oxide layer, and wherein forming the isolation structure comprises:
forming an electrode in the central part of the outermost trench, the electrode being separated from the epitaxial layer or layer stack by the oxide layer and the contiguous region of oxidized semiconductor material.

16. The method of claim 1 , wherein forming the isolation structure comprises:
forming a mask on the epitaxial layer or layer stack, the mask covering the first region of the epitaxial layer or layer stack and having an opening that exposes the second region of the epitaxial layer or layer stack;
implanting oxygen atoms into the second region of the epitaxial layer or layer stack through the opening in the mask to form a buried oxide layer in the second region of the epitaxial layer or layer stack;
etching a plurality of trenches into the second region of the epitaxial layer or layer stack, wherein an outermost trench of the plurality of trenches surrounds the other trenches and laterally delimits the second region of the epitaxial layer or layer stack; and
forming an oxide layer on sidewalls of the trenches and that connects to the buried oxide layer.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Ma Ling
• Haase Robert
• Henson Timothy

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/051

  of isolation region based on field-effect · CPC title

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H10W10/01

  Manufacture or treatment · CPC title