Standard and engineering change order (ECO) cell regions and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-12199037-B2
Application number	US-202318362824-A
Country	US
Kind code	B2
Filing date	Jul 31, 2023
Priority date	Nov 29, 2016
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.

First claim

What is claimed is:

1. A semiconductor device comprising an array of cell regions in which at least one of the cell regions includes:
first and second active areas, in a semiconductor substrate, having corresponding long axes in a first direction;
first, third and fifth conductive structures overlapping the first active area and having corresponding long axes in a second direction different from the first direction,
the first conductive structure being a first gate structure and being between the third and fifth conductive structures;

second, fourth and sixth conductive structures overlapping the second active area and having corresponding long axes in the second direction,
the second conductive structure being a second gate structure and being between the fourth and sixth conductive structures, and
the long axes of the first and second conductive structures being substantially collinear; and

a seventh conductive structure overlapping one of the first conductive structure or the second conductive structure,
the seventh conductive structure being over a first gap between the third and fourth conductive structures or a second gap between the fifth and sixth conductive structures.

2. The semiconductor device of claim 1 , further comprising:
a first via over and within a region bounded by the seventh conductive structure; and
an eighth conductive structure over the first via and sized so as to substantially completely overlap the first via,
the eighth conductive structure being a segment within a first metallization layer.

3. The semiconductor device of claim 1 , wherein:
the long axes of the first and second active areas extend parallel to, and are disposed on opposite sides of, a first axis of symmetry, and
ends of the first through sixth conductive structures, in the second direction, extend correspondingly beyond the first and second active areas away from the first axis of symmetry.

4. The semiconductor device of claim 3 , wherein:
the ends of the third through sixth conductive structures, in the second direction, extend beyond corresponding ones of the ends of the first and second conductive structures.

5. The semiconductor device of claim 3 , further comprising:
one or more second vias; and wherein
each second via partially overlaps a corresponding corner of the corresponding end of a corresponding one of the fourth conductive structure or the fifth conductive structure.

6. The semiconductor device of claim 5 , wherein:
each second via is sized so as to extend beyond the corresponding corner of the corresponding end of the corresponding one of the fourth conductive structure or the fifth conductive structure in at least the second direction.

7. The semiconductor device of claim 1 , wherein:
the first and second conductive structures, for at least one of the cell regions, represent a unitary gate structure, and
the seventh conductive structure contacts the unitary gate structure.

8. The semiconductor device of claim 1 , wherein:
the long axes of the first and second active areas extend parallel to, and are disposed on opposite sides of, a first axis of symmetry,
a third gap is asymmetrically between the first and second conductive structures relative to the first axis of symmetry, and
the seventh conductive structure is in contact with the one of the first conductive structure or the second conductive structure in a location proximate to the third gap.

9. The semiconductor device of claim 1 , wherein:
the long axes of the first and second active areas extend parallel to, and are disposed on opposite sides of, a first axis of symmetry, and
the seventh conductive structure is asymmetric about the first axis of symmetry.

10. The semiconductor device of claim 1 , wherein:
the substantially collinear long axes of the first and second conductive structures represent a second axis of symmetry; and
the seventh conductive structure is asymmetric about the second axis of symmetry.

11. A semiconductor device comprising an array of cell regions in which at least one cell includes:
first and second active areas, in a semiconductor substrate, having corresponding long axes in a first direction;
a first conductive structure overlapping the first and second active areas and having a long axis in a second direction different from the first direction;
second and fourth conductive structures overlapping the first active area and having long axes in the second direction,
the first conductive structure being between the second and fourth conductive structures;

third and fifth conductive structures overlapping the second active area and having long axes in the second direction,
the first conductive structure being a first gate structure and being between the third and fifth conductive structures; and

a sixth conductive structure overlapping the first conductive structure,
the sixth conductive structure being over a first gap between the second and third conductive structures or a second gap between the fourth and fifth conductive structures.

12. The semiconductor device of claim 11 , further comprising:
a first via over and within a region bounded by the sixth conductive structure; and
a seventh conductive structure over the first via and sized so as to substantially completely overlap the first via,
the seventh conductive structure being a segment within a first metallization layer.

13. The semiconductor device of claim 11 , wherein:
the long axes of the first and second active areas extend parallel to, and are disposed on opposite sides of, a first axis of symmetry, and
ends of the first through fifth conductive structures, in the second direction, extend correspondingly beyond the first and second active areas away from the first axis of symmetry.

14. The semiconductor device of claim 13 , wherein:
the ends of the second through fifth conductive structures, in the second direction, extend beyond the end of the first conductive structure.

15. The semiconductor device of claim 13 , further comprising:
one or more second vias; and wherein
each second via partially overlaps a corresponding corner of the corresponding end of a corresponding one of the third conductive structure or the fourth conductive structure.

16. The semiconductor device of claim 15 , wherein:
each second via is sized so as to extend beyond the corresponding corner of the corresponding end of the corresponding one of the third conductive structure or the fourth conductive structure in at least the second direction.

17. The semiconductor device of claim 11 , wherein:
the long axes of the first and second active areas extend parallel to, and are disposed on opposite sides of, a first axis of symmetry,
the sixth conductive structure is asymmetric about the first axis of symmetry,
the sixth conductive structure is asymmetric about the long axis of the first conductive structure, and
the sixth conductive structure is in contact with the first conductive structure.

18. A semiconductor device comprising an array of cell regions in which at least one cell includes:
first and second active areas, in a semiconductor substrate, having corresponding long axes in a first direction;
first, third and fifth conductive structures overlapping the first active area and having corresponding long axes in a second direction different from the first direction,
the first conductive structure being between the third and fifth conductive structures, and
the first conductive structure extends across an entire height, in the second direction,

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tien Li-Chun
• Chen Shun Li
• Chiang Ting-Wei
• Chen ting yu
• Wang Xinyong

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D84/00 Primary

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title