Pixel circuit, driving method, display substrate and display device

US12198634B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12198634-B2
Application numberUS-202117801513-A
CountryUS
Kind codeB2
Filing dateSep 29, 2021
Priority dateSep 29, 2021
Publication dateJan 14, 2025
Grant dateJan 14, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides a display substrate and a display device. The display substrate includes a driving circuit, a light-emitting element, a first light-emitting control circuit, a first control circuit, a second control circuit, a third control circuit, a data writing-in circuit and an energy storage circuit. The first control circuit is configured to control to connect the first voltage line and a first end of the light-emitting element under the control of the first control signal; the second control circuit is configured to control to connect the reference voltage line and the second end of the light-emitting element under the control of a second control signal; the third control circuit is configured to control to connect the first end of the energy storage circuit and the control end of the driving circuit under the control of a third control signal.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel circuit, comprising a driving circuit, a light-emitting element, a first light-emitting control circuit, a first control circuit, a second control circuit, a third control circuit, a data writing-in circuit and an energy storage circuit, wherein the first control circuit is electrically connected to a first control line, a first voltage line and a second end of the driving circuit, respectively, and is configured to control to connect the first voltage line and a first end of the light-emitting element under the control of a first control signal provided by the first control line; the first light-emitting control circuit is respectively electrically connected to a first light-emitting control line, a second end of the light-emitting element and the first voltage line, and is configured to control to connect the second end of the light-emitting element and the first voltage line under the control of a first light-emitting control signal provided by the first light-emitting control line; the second control circuit is electrically connected to a second control line, a reference voltage line and the second end of the light-emitting element, respectively, is configured to control to connect the reference voltage line and the second end of the light-emitting element under the control of a second control signal provided by the second control line; the third control circuit is electrically connected to a third control line, a first end of the energy storage circuit and a control end of the driving circuit, respectively, and is configured to control to connect the first end of the energy storage circuit and the control end of the driving circuit under the control of a third control signal provided by the third control line; the data writing-in circuit is electrically connected to a scan line, a data line and the first end of the energy storage circuit, respectively, and is configured to control to write a data voltage on the data line into the first end of the energy storage circuit under the control of a scan signal provided by the scan line; a second end of the energy storage circuit is electrically connected to a first end of the driving circuit, and the energy storage circuit is used for storing electrical energy; the second end of the driving circuit is electrically connected to the first end of the light-emitting element; the driving circuit is configured to control to connect the first end of the driving circuit and the second end of the driving circuit under the control of a potential of the control end of the driving circuit; the pixel circuit further comprises: a second light-emitting control circuit and an initial control circuit; wherein the second light-emitting control circuit is respectively electrically connected to a second light-emitting control line, a second voltage line and the first end of the driving circuit, and is configured to control to connect the first end of the driving circuit and the second voltage line under the control of a second light-emitting control signal provided by the second light-emitting control line; the initial control circuit is respectively electrically connected to an initial control line, and the control end of the driving circuit and the reference voltage line, is configured to connect the reference voltage line and the control end of the driving circuit under the control of an initial control signal provided by the initial control line; wherein the scan line and the initial control line are the same signal line. 2. The pixel circuit according to claim 1 , wherein transistors included in the pixel circuit are all p-type transistors, and the third control line and the first light-emitting control line are a same signal line; the first control line, the second control line, the scan line, and the initial control line are a same signal line. 3. The pixel circuit according to claim 2 , wherein the second light-emitting control circuit includes a sixth transistor, and the initial control circuit includes a seventh transistor; a control electrode of the sixth transistor is electrically connected to the second light-emitting control line, a first electrode of the sixth transistor is electrically connected to the second voltage line, and a second electrode of the sixth transistor is electrically connected to the first electrode of the driving transistor; a control electrode of the seventh transistor is electrically connected to the initial control line, a first electrode of the seventh transistor is electrically connected to the reference voltage line, and a second electrode of the seventh transistor is electrically connected to the control end of the driving circuit. 4. The pixel circuit according to claim 2 , wherein the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the first light-emitting control circuit includes a third transistor; a control electrode of the first transistor is electrically connected to the first control line, a first electrode of the first transistor is electrically connected to the first voltage line, and a second electrode of the first transistor is electrically connected to the second end of the driving circuit; a control electrode of the second transistor is electrically connected to the second control line, a first electrode of the second transistor is electrically connected to the reference voltage line, and a second electrode of the second transistor is electrically connected to the second end of the light-emitting element; a control electrode of the third transistor is electrically connected to the first light-emitting control line, a first electrode of the third transistor is electrically connected to the first voltage line, and a second electrode of the third transistor is electrically connected to the second end of the light-emitting element. 5. The pixel circuit according to claim 2 , wherein the third control circuit includes a fourth transistor, the data writing-in circuit includes a fifth transistor, and the energy storage circuit includes a storage capacitor; a control electrode of the fourth transistor is electrically connected to the third control line, a first electrode of the fourth transistor is electrically connected to a first end of the storage capacitor, and a second electrode of the fourth transistor is electrically connected to the control end of the driving circuit; a control electrode of the fifth transistor is electrically connected to the scan line, a first electrode of the fifth transistor is electrically connected to the data line, and a second electrode of the fifth transistor is electrically connected to the first end of the storage capacitor; a second end of the storage capacitor is electrically connected to the first end of the driving circuit. 6. The pixel circuit according to claim 1 , wherein transistors included in the first light-emitting control circuit and transistors included in the second light-emitting control circuit are p-type transistors; transistors included in the third control circuit are p-type transistors, the transistors included in the second control circuit are n-type transistors; the first light-emitting control line, the second light-emitting control line, the second control line and the third control line are a same signal line; transistors included in the data writing-in circuit are n-type transistors, transistors included in the initial control circuit are n-type transistors, and the scan line and the initial control line are a same signal line. 7. The pixel circuit according to claim 1 , wherein the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the first light-emitting control circuit inclu

Assignees

Inventors

Classifications

  • using an active matrix · CPC title

  • with pixel circuitry controlling the current through the light-emitting element · CPC title

  • Power management, e.g. power saving · CPC title

  • Preventing or counteracting the effects of ageing · CPC title

  • Details of timing specific for flat panels, other than clock recovery · CPC title

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Frequently asked questions

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What does patent US12198634B2 cover?
The present disclosure provides a display substrate and a display device. The display substrate includes a driving circuit, a light-emitting element, a first light-emitting control circuit, a first control circuit, a second control circuit, a third control circuit, a data writing-in circuit and an energy storage circuit. The first control circuit is configured to control to connect the first vo…
Who is the assignee on this patent?
Chongqing Boe Display Tech Co Ltd, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3258. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 14 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).