Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12198601-B2
Application number	US-202218027111-A
Country	US
Kind code	B2
Filing date	Mar 21, 2022
Priority date	Mar 21, 2022
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

First claim

What is claimed is:

1. A display substrate, comprising a base substrate and a driving circuit arranged on the base substrate; wherein the driving circuit comprises multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node;
wherein a length of a channel of each of at least a part of the denoising transistors is a first length L 1 ;
a length of a channel of each of at least a part of the multiple transistors for driving is a second length L 2 ; and
the first length L 1 is not equal to the second length L 2 .

2. The display substrate according to claim 1 , wherein the first length L 1 is greater than the second length L 2 .

3. The display substrate according to claim 2 , wherein the first length L 1 is greater than or equal to 5.5 μm and smaller than or equal to 9 μm, the second length L 2 is greater than or equal to 2 μm and smaller than or equal to 5.0 μm, and a ratio of the first length L 1 to the second length L 2 is greater than or equal to 1.1 and smaller than or equal to 4.5.

4. The display substrate according to claim 1 , wherein the driving circuit further comprises a transistor for denoising a carry signal output end, and a transistor for denoising a driving signal output end;
a length of a channel of the transistor for denoising the carry signal output end is a third length L 3 ;
a length of a channel of the transistor for denoising the driving signal output end is a fourth length L 4 ; and
the third length L 3 is not equal to the second length L 2 , and the fourth length L 4 is not equal to the second length L 2 .

5. The display substrate according to claim 4 , wherein the third length L 3 is greater than the second length L 2 , and the fourth length is greater than the second length L 2 .

6. The display substrate according to claim 5 , wherein the third length L 3 is greater than or equal to 5.5 μm and smaller than or equal to 9 μm, the fourth length L 4 is greater than or equal to 5.5 μm and smaller than or equal to 9 μm, the second length L 2 is greater than or equal to 2 μm and smaller than or equal to 5.0 μm, a ratio of the third length L 3 to the second length L 2 is greater than or equal to 1.1 and smaller than or equal to 4.5, and a ratio of the fourth length L 4 to the second length L 2 is greater than or equal to 1.1 and smaller than or equal to 4.5.

7. The display substrate according to claim 1 , wherein the transistors for driving comprise a transistor for driving the pull-up node, a transistor for driving a carry signal output end, and a transistor for driving a driving signal output end.

8. The display substrate according to claim 1 , wherein the driving circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, and the first transistor, the second transistor, the third transistor and the fourth transistor are the denoising transistors;
a control electrode of the first transistor is electrically connected to a pull-up resetting end, a first electrode of the first transistor is electrically connected to the pull-up node, and a second electrode of the first transistor is electrically connected to a first voltage end;
a control electrode of the second transistor is electrically connected to a first pull-down node, a first electrode of the second transistor is electrically connected to the pull-up node, and a second electrode of the second transistor is electrically connected to the first voltage end;
a control electrode of the third transistor is electrically connected to a second pull-down node, a first electrode of the third transistor is electrically connected to the pull-up node, and a second electrode of the third transistor is electrically connected to the first voltage end; and
a control electrode of the fourth transistor is electrically connected to an ON voltage end, a first electrode of the fourth transistor is electrically connected to the pull-up node, and a second electrode of the fourth transistor is electrically connected to the first voltage end.

9. The display substrate according to claim 8 , wherein the driving circuit comprises a fifth transistor and a sixth transistor, and the fifth transistor and the sixth transistor are the denoising transistors;
a control electrode of the fifth transistor is electrically connected to the pull-up node, a first electrode of the fifth transistor is electrically connected to a first pull-down control node, and a second electrode of the fifth transistor is electrically connected to the first voltage end; and
a control electrode of the sixth transistor is electrically connected to the pull-up node, a first electrode of the sixth transistor is electrically connected to a second pull-down control node, and a second electrode of the sixth transistor is electrically connected to the first voltage end.

10. The display substrate according to claim 9 , wherein at least one of a length of a channel of the first transistor, a length of a channel of the second transistor, a length of a channel of the third transistor, a length of a channel of the fourth transistor, a length of a channel of the fifth transistor, and a length of a channel of the sixth transistor is the first length L 1 .

11. The display substrate according to claim 8 , wherein the driving circuit further comprises a seventh transistor, an eighth transistor and a ninth transistor, and the seventh transistor, the eighth transistor and the ninth transistor are the driving transistors for driving;
a control electrode of the seventh transistor is electrically connected to the pull-up node, a first electrode of the seventh transistor is electrically connected to a clock signal end, and a second electrode of the seventh transistor is electrically connected to the driving signal output end;
a control electrode of the eighth transistor is electrically connected to the pull-up node, a first electrode of the eighth transistor is electrically connected to the clock signal end, and a second electrode of the eighth transistor is electrically connected to a carry signal output end; and
a control electrode of the ninth transistor is electrically connected to a first input end, a first electrode of the ninth transistor is electrically connected to a second input end, and a second electrode of the ninth transistor is electrically connected to the pull-up node.

12. The display substrate according to claim 11 , wherein at least one of a length of a channel of the seventh transistor, a length of a channel of the eighth transistor, and a length of a channel of the ninth transistor is the second length L 2 .

13. The display substrate according to claim 11 , wherein the driving circuit further comprises a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;
a control electrode of the tenth transistor is electrically connected to the first pull-down node, a first electrode of the tenth transistor is electrically connected to a driving signal output end, and a second electrode of the tenth transistor is electrically connected to a second voltage end;
a control electrode of the eleventh transistor is electrically connected to the second pull-down node, a first electrode of the eleventh transistor is electrically connected to the driving signal output end, and a second electrode of the eleventh transistor is electrically connected to the second voltage end;
a control electrode of the twelfth transistor is electrically connected to the first pull-down node, a first electrode of the twelfth transistor is electrically connected to th

Assignees

• Hefei Boe Display Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Liu Qi
• Zhang Chunxu
• Liu Jiantao
• Guo Lei
• Zhou Maoxiu
• Cheng Min
• Jiang Xiaoting

Classifications

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title