Frequency allocation in multi-qubit circuits

Patent metadata

Field	Value
Publication number	US-12198008-B2
Application number	US-202318331465-A
Country	US
Kind code	B2
Filing date	Jun 8, 2023
Priority date	Jun 7, 2018
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Techniques facilitating frequency allocation in multi-qubit circuits are provided. In one example, a computer-implemented method comprises determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.

First claim

What is claimed is:

1. A system comprising:
a memory that stores computer executable components; and
a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise:
a performance analysis component that analyzes simulated performance of respective qubit chip features and determines operation metrics for the respective qubit chip features at respective frequency offsets; and
a fabrication component that fabricates a superconducting qubit chip using one or more of the respective qubit chip features based on the respective operation metrics determined by the performance analysis component.

2. The system of claim 1 , wherein the respective qubit chip features comprise at least one of total number of qubits, functionality of respective qubits, or a number of qubits per bus.

3. The system of claim 1 , wherein the respective qubit chip features comprise at least one of operational frequency ranges for respective qubits or anharmonicity parameters associated with the respective qubits.

4. The system of claim 1 , wherein the computer executable components further comprise:
a collision monitoring component that defines frequency collision windows for respective qubits corresponding to the qubit chip features.

5. The system of claim 4 , wherein the collision monitoring component identifies collisions between the respective qubits based on the frequency collision windows.

6. The system of claim 1 , wherein the computer executable components further comprise:
a design generation component that generates a superconducting qubit chip design using one or more of the respective qubit chip features based on the respective operation metrics determined by the performance analysis component.

7. A computer-implemented method comprising:
determining, by a device operatively coupled to a processor, operation metrics for respective qubit chip features by analyzing simulated performance of the respective qubit chip features at respective frequency offsets; and
fabricating, by the device, a superconducting qubit chip using one or more of the respective qubit chip features based on their respectively corresponding operation metrics.

8. The computer-implemented method of claim 7 , wherein the determining comprises:
defining, by the device, frequency collision windows for respective qubits corresponding to the qubit chip features.

9. The computer-implemented method of claim 8 , wherein the determining further comprises:
identifying, by the device, collisions between the respective qubits based on the frequency collision windows.

10. The computer-implemented method of claim 7 , wherein the fabricating of a superconducting qubit chip, further comprises:
generating, by the device, a superconducting qubit chip design using one or more of the respective qubit chip features based on their respectively corresponding operation metrics.

11. The computer-implemented method of claim 7 , wherein the respective qubit chip features comprise at least one of total number of qubits, functionality of respective qubits, or a number of qubits per bus.

12. The computer-implemented method of claim 7 , wherein the respective qubit chip features comprise at least one of operational frequency ranges for respective qubits or anharmonicity parameters associated with the respective qubits.

13. The computer-implemented method of claim 7 , further comprising fabricating a superconducting qubit chip with improved resilience to imperfections in fabrication.

14. A computer program product for fabricating a superconducting qubit chip, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
determine, by a device operatively coupled to a processor, operation metrics for respective qubit chip features by analyzing simulated performance of the respective qubit chip features at respective frequency offsets; and
fabricate, by the device, a superconducting qubit chip using one or more of the respective qubit chip features based on their respectively corresponding operation metrics.

15. The computer program product of claim 14 , wherein the program instructions further cause the processor to:
define, by the device, frequency collision windows for respective qubits corresponding to the qubit chip features.

16. The computer program product of claim 14 , wherein the program instructions further cause the processor to:
identify, by the device, collisions between the respective qubits based on the frequency collision windows.

17. The computer program product of claim 14 , wherein the program instructions further cause the processor to:
generate, by the device, a superconducting qubit chip design using one or more of the respective qubit chip features based on their respectively corresponding operation metrics.

18. The computer program product of claim 14 , wherein the respective qubit chip features comprise at least one of total number of qubits, functionality of respective qubits, or a number of qubits per bus.

19. The computer program product of claim 14 , wherein the respective qubit chip features comprise at least one of operational frequency ranges for respective qubits or anharmonicity parameters associated with the respective qubits.

20. The computer program product of claim 14 , wherein the program instructions further cause the processor to:
fabricate a superconducting qubit chip with improved resilience to imperfections in fabrication.

Assignees

• IBM

Inventors

• Hertzberg Jared Barney
• Rosenblatt Sami
• Magesan Easwar
• Smolin John Aaron

Classifications

• G06N10/00 Primary

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• H10N99/05

  Devices based on quantum mechanical effects, e.g. quantum interference devices or metal single-electron transistors · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title