Systems and methods for testing cxl enabled devices in parallel

Patent metadata

Field	Value
Publication number	US-12197303-B2
Application number	US-202318129414-A
Country	US
Kind code	B2
Filing date	Mar 31, 2023
Priority date	Sep 21, 2022
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing flexible and independent parallel testing across the plurality of DUTs. In one exemplary implementation, the tester generates and manages workloads independently for DUTs included in the plurality of DUTs. The DUTs can be memory devices the tester is configured to test different memory spaces in parallel. The different memory spaces can have various implementations (e.g., included in the plurality of DUTs, different memory spaces are within one of the DUTs included in the plurality of DUTs, etc.). Workloads can be generated based upon individual characteristics of the DUTS and managed separately. The testing can include performance testing. (e.g., bandwidth testing, latency testing, error testing, etc.).

First claim

The invention claimed is:

1. A test system comprising:
a user interface configured to enable user interaction with the system;
a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the plurality of DUTs are compute express link (CXL) protocol compliant; and
a tester configured to direct testing of the plurality of DUTs, wherein the tester manages flexible independent and parallel testing of the plurality of DUTs, wherein the tester generates workloads independently for respective ones of the plurality of DUTs and the workloads are generated based upon individual characteristics of the respective ones or the plurality of DUTs, and wherein the tester manages workloads separately and independently for the respective ones of the plurality of DUTs.

2. The test system of claim 1 , wherein the plurality of DUTs comprises memory devices and the tester is configured to test different memory spaces in parallel, and the different memory spaces are included in the plurality of DUTs.

3. The test system of claim 1 , wherein the plurality of DUTs are memory devices the tester is configured to test different memory spaces in parallel and the different memory spaces are within the respective ones of the plurality of DUTs.

4. The test system of claim 1 , wherein the testing comprises performance testing, bandwidth testing, latency testing, and error testing.

5. The test system of claim 1 , wherein the tester prevents interference with the testing of the respective ones of the plurality of devices.

6. The test system of claim 1 , wherein memory locations associated with isolation and mapping of the respective ones of the plurality of DUTs are flushed when the respective ones of the plurality of DUTs are removed.

7. The test system of claim 1 , wherein the tester assures a sequence of commands prevent a host CPU from issuing replacement commands when the replacement commands otherwise detrimentally impact test results.

8. A test method comprising:
directing parallel testing of a plurality of devices under test (DUTs), wherein the testing comprises compute express link (CXL) protocol communication with the plurality of DUTs; and
preventing testing operations of the plurality of DUTs from detrimentally interfering with one another, wherein the testing operations are performed in accordance with user directed percentage of reads and writes.

9. The test method of claim 8 , wherein the directing parallel testing of the plurality of DUTs comprises managing testing workloads independently.

10. The test method of claim 8 , wherein user configuration requirements are mapped to characteristics of the plurality of DUTs.

11. The test method of claim 8 , wherein the testing is performed on a system level rather than component level.

12. The test method of claim 8 , wherein the plurality of DUTs comprise a CXL type 3 memory expansion device.

13. The test method of claim 8 , wherein the directing comprises testing of randomly generated address locations within respective ones of the plurality of DUTs.

14. A test system comprising:
a user interface configured to enable user interaction with the system;
a test board configured to communicatively couple with a device under test (DUT), wherein the DUT is compliant with a compute express link (CXL) protocol; and
a tester configured to direct testing of the DUT, wherein the tester manages testing of the DUT, wherein the tester is configured to launch a plurality of test threads, wherein the plurality of threads corresponds to respective plurality of ranges in the DUT, and wherein the tester is configured to manage the testing of the respective plurality of ranges in the DUT in a flexible and independent parallel manner.

15. The test system of claim 14 , wherein the testing is based upon independent workload generation for the respective plurality of test threads.

16. The test system of claim 14 , wherein the testing comprises performance testing.

17. The test system of claim 14 , wherein user configuration requirements are mapped to characteristics of the DUT.

Assignees

• Advantest Corp

Inventors

• Malisic Srdjan
• Yuan Chi

Classifications

• G06F11/263 Primary

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

• G06F11/2221

  to test input/output devices or peripheral units · CPC title

• G06F11/273

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title

• G06F11/2733

  Test interface between tester and unit under test · CPC title

• G06F11/2273 Primary

  Test methods · CPC title