Array substrate, liquid crystal display panel, and display device having trapezoidal shaped electrode

Patent metadata

Field	Value
Publication number	US-12197088-B2
Application number	US-202217635839-A
Country	US
Kind code	B2
Filing date	Feb 10, 2022
Priority date	Jan 12, 2022
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

An array substrate includes a first electrode. The first electrode includes first, second, third and fourth side walls and first and second bottom walls. Ends of the third and fourth side walls are connected by the second bottom wall. A shortest distance d 1 is from the first bottom wall to the second bottom wall. A distance d 2 is from an end of the first side wall away from the second side wall to an end of the third side wall away from the fourth side wall. A distance d 3 is from an end of the second side wall away from the first side wall to an end of the fourth side wall away from the third side wall, and d 1 <d 2 , d 1 <d 3.

First claim

What is claimed is:

1. An array substrate, comprising:
a driving circuit layer and a first electrode located on the driving circuit layer; wherein the driving circuit layer comprises a plurality of scan lines and a plurality of data lines; wherein an extension direction of the scan lines is defined as a first direction, and an extension direction of the data lines as a second direction, the second direction is perpendicular to the first direction; wherein the first electrode further comprises a solid part; wherein the solid part further comprises:
a first side wall, a second side wall, and a first bottom wall; an end of the first side wall and an end of the second side wall are connected by the first bottom wall; and
a third side wall, a fourth side wall, and a second bottom wall; an end of the third side wall and an end of the fourth side wall are connected by the second bottom wall;
wherein a connecting line from an end of the first side wall away from the second side wall to an end of the third side wall away from the fourth side wall and a connecting line from an end of the second side wall away from the first side wall to an end of the fourth side wall away from the third side wall extends along the first direction;
wherein a shortest distance from the first bottom wall to the second bottom wall is defined as d 1 , a distance from the end of the first side wall away from the second side wall to the end of the third side wall away from the fourth side wall is defined as d 2 , a distance from the end of the second side wall away from the first side wall to the end of the fourth side wall away from the third side wall is defined as d 3 , and d 1 <d 2 and d 1 <d 3 ;
wherein a plurality of sub-pixel areas are surrounded by the plurality of scan lines and the plurality of data lines, the first electrode is located in the sub-pixel area;
wherein the solid part of the first electrode comprises two opposite trapezoidal electrode portions, an intermediate connection portion, and a cap electrode portion, each of the trapezoidal electrode portions comprises a narrow base and a broad base opposite to the narrow base, the narrow bases of the trapezoidal electrode portions face each other, the intermediate connection portion is formed between and connected to the narrow bases of the trapezoidal electrode portions, the cap electrode portion is formed on the broad base of one of the trapezoidal electrode portions, the broad base of the other of the trapezoidal electrode portions is a free distal end of the solid part, and a width of the cap electrode portion is greater of a width of each of the trapezoidal electrode portions and a width of the intermediate connection portion.

2. The array substrate according to claim 1 , wherein the first electrode further comprises a cavity located in the solid part, the first side wall, the second side wall, the third side wall, the fourth side wall, the first bottom wall, and the second bottom wall are inner walls of the cavity.

3. The array substrate according to claim 2 , wherein the solid part further comprises an outer side wall, the outer side wall is arranged around the first side wall, the second side wall, the third side wall, and the fourth side wall, and the outer side wall is the outer wall of the solid part.

4. The array substrate according to claim 2 , wherein the first electrode is a common electrode.

5. The array substrate according to claim 1 , wherein the first electrode is a pixel electrode.

6. The array substrate according to claim 1 , wherein an angle between the connecting line between the end of the first side wall connected to the first bottom wall and the end of the third side wall connected to the second bottom wall and the first direction is greater than 0 degrees.

7. The array substrate according to claim 1 , wherein an angle between the first side wall and the second direction is defined as a first inclination angle θ 1 , an angle between the second side wall and the second direction is defined as a second inclination angle θ 2 , an angle between the third side wall and the second direction is defined as a third inclination angle θ 3 , an angle between the fourth side wall and the second direction is defined as a fourth inclination angle θ 4 , and value ranges of θ 1 , θ 2 , θ 3 , and θ 4 are all 3 degrees to 35 degrees.

8. The array substrate according to claim 7 , wherein the value ranges of θ 1 , θ 2 , θ 3 , and θ 4 are all 5 degrees to 15 degrees.

9. The array substrate according to claim 7 , wherein the first side wall is parallel to the fourth side wall, and the second side wall is parallel to the third side wall; θ 1 and θ 4 are the first inclination angles of the first electrode, θ 2 and θ 3 are the second inclination angles of the first electrode; θ 1 , θ 2 , θ 3 , and θ 4 satisfy: θ 1 =θ 4 and θ 2 =θ 3 .

10. The array substrate according to claim 9 , wherein θ 1 is equal to or not equal to θ 2 , and θ 3 is equal to or not equal to θ 4 .

11. The array substrate according to claim 7 , wherein θ 1 ≠θ 2 and θ 3 ≠θ 4 .

12. The array substrate according to claim 7 , wherein the solid part further comprises:
a first bottom wall, wherein two ends of the first bottom wall are respectively connected with the first side wall and the second side wall; and
a second bottom wall, wherein two ends of the second bottom wall are respectively connected with the third side wall and the fourth side wall.

13. The array substrate according to claim 12 , wherein the first bottom wall and the second bottom wall are both planes parallel to the second direction or not parallel to the second direction.

14. The array substrate according to claim 12 , wherein the first bottom wall and the second bottom wall are both curved surfaces.

15. The array substrate according to claim 1 , wherein the solid part further comprises:
a fifth side wall connected to the end of the first side wall away from the second side wall; and
a sixth side wall, connected to the end of the third side wall away from the fourth side wall;
an angle between the fifth side wall and the second direction is defined as a fifth inclination angle β 1 , an angle between the sixth side wall and the second direction is a sixth inclination angle β 2 , and value ranges of β 1 and β 2 are both 0 degrees to 90 degrees.

16. The array substrate according to claim 15 , wherein the value ranges of β 1 and β 2 are both 45 degrees to 60 degrees.

17. The array substrate according to claim 15 , wherein the solid part further comprises:
a seventh side wall connected to the fifth side wall and the sixth side wall, respectively; and
an eighth side wall connected to the second side wall and the fourth side wall, respectively;
wherein the eighth side wall and the seventh side wall are located at two ends of the solid part.

18. The array substrate according to claim 1 , wherein the array substrate further comprises a substrate and a second electrode opposite to the first electrode, the second electrode is located within the driving circuit layer or on the driving circuit layer, the driving circuit layer is located on the substrate, and the second electrode is located between the substrate and the first electrode.

19. A liquid crystal display panel, comprising:
liquid crystal and a color filter substrate, wherein the liquid crystal display panel further comprises an array substrate, and the liquid crystal is located between the color filter substrate and the array substrate; wherein the array substrate comprises a driving circuit layer and a

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Wu Yunfei
• Li Yongkai
• Tan Cong

Classifications

• G02F1/134372

  for fringe field switching [FFS] where the common electrode is not patterned · CPC title

• G02F1/134363

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/133514

  Colour filters · CPC title

• G02F1/1343 Primary

  Electrodes {(reflective electrodes G02F1/133553)} · CPC title