Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12193282-B2
Application number	US-202017419749-A
Country	US
Kind code	B2
Filing date	Sep 10, 2020
Priority date	Jun 5, 2020
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

A display substrate and a display device. In the display substrate, at least one of the inter-opening region, the first opening peripheral region and the second opening peripheral region includes a first virtual sub-pixel; the first signal line extends along a first direction and includes a first portion passing through the first opening peripheral region, the inter-opening region and the second opening peripheral region; the first portion passes through the first virtual sub-pixel, and the first virtual sub-pixel includes a first compensation capacitor, a first plate of the first compensation capacitor is in a same layer as the first portion of the first signal line and electrically connected with the first portion of the first signal line, and in a same layer as the second plate of the storage capacitor; the second plate is in a different layer from, insulated from, and overlaps with the first plate.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate, comprising:
a first opening region comprising a first opening and a first opening peripheral region surrounding the first opening;
a second opening region which is adjacent to the first opening region in a first direction and comprises a second opening and a second opening peripheral region surrounding the second opening;
an inter-opening region between the first opening region and the second opening region, wherein at least one selected from a group consisting of the inter-opening region, the first opening peripheral region, and the second opening peripheral region comprises a first dummy sub-pixel;
a display region which at least partially surrounds the first opening region, the second opening region, and the inter-opening region, and comprises a plurality of pixels, wherein each of the plurality of pixels comprises a plurality of sub-pixels, each of the plurality of sub-pixels comprises a pixel circuit, and the pixel circuit comprises:
a transistor comprising an active layer, a gate electrode, and a source electrode and a drain electrode;
a light-emitting element connected with one of the source electrode and the drain electrode of the transistor; and
a storage capacitor comprising a first electrode plate and a second electrode plate, wherein the gate electrode and the first electrode plate of the storage capacitor are in a same layer; and

a first signal line which extends in the first direction, comprises a first portion passing through the first opening peripheral region, the inter-opening region, and the second opening peripheral region, and is configured to provide a first display signal to the pixel circuit, wherein the first portion of the first signal line passes through the first dummy sub-pixel, the first dummy sub-pixel comprises a virtual pixel circuit, the virtual pixel circuit comprises a first compensation capacitor, and the first compensation capacitor comprises:
a first electrode plate which is in a same layer as the first portion of the first signal line and electrically connected with the first signal line, and is in a same layer as the second electrode plate of the storage capacitor; and
a second electrode plate which is in a different layer and insulated from the first electrode plate of the first compensation capacitor, wherein an orthographic projection of the second electrode plate of the first compensation capacitor on the base substrate at least partially overlaps with an orthographic projection of the first electrode plate of the first compensation capacitor on the base substrate, wherein

the first electrode plate of the first compensation capacitor comprises:
a first extension portion which is connected with the first portion of the first signal line, extends from the first portion of the first signal line and is at a first side of the first portion of the first signal line in a second direction intersecting with the first direction; and
a second extension portion which is connected with the first portion of the first signal line, extends from the first portion of the first signal line and is at a second side of the first portion of the first signal line opposite to the first side in the second direction.

2. The display substrate according to claim 1 , wherein the first extension portion, the second extension portion, and the first portion of the first signal line are integrated.

3. The display substrate according to claim 1 , wherein a material of the second electrode plate of the first compensation capacitor comprises a semiconductor material, and the second electrode plate is in a same layer as the active layer.

4. The display substrate according to claim 1 , wherein the virtual pixel circuit further comprises a second compensation capacitor, and the second compensation capacitor comprises:
a first electrode plate, wherein the first electrode plate of the first compensation capacitor also serves as the first electrode plate of the second compensation capacitor; and
a second electrode plate which is in a different layer from and insulated from the first electrode plate of the second compensation capacitor, and is in a same layer as the source electrode and the drain electrode, wherein
an orthographic projection of the second electrode plate of the second compensation capacitor on the base substrate at least partially overlaps with an orthographic projection of the first electrode plate of the second compensation capacitor on the base substrate.

5. The display substrate according to claim 4 , wherein the second electrode plate of the second compensation capacitor is electrically connected with the second electrode plate of the first compensation capacitor.

6. The display substrate according to claim 5 , further comprising:
a first power line, wherein the first power line is connected with a first voltage terminal, configured to provide a first power supply voltage to the pixel circuit, and connected with the second electrode plate of the storage capacitor, and the first power line comprises:
a plurality of first sub-routing lines extending along the first direction; and
a plurality of second sub-routing lines that extend along a second direction intersecting with the first direction and are electrically connected with the plurality of first sub-routing lines, wherein
a first part of second sub-routing line of the plurality of second sub-routing lines passes through the inter-opening region and passes through the first dummy sub-pixel, the second electrode plate of the second compensation capacitor comprises a first portion and a second portion, the first part of second sub-routing line is in a same layer as the first portion of the second electrode plate of the second compensation capacitor and electrically connected with the first portion of the second electrode plate to serve as the second portion of the second electrode plate of the second compensation capacitor, and the first part of second sub-routing line is electrically connected with the second electrode plate of the first compensation capacitor.

7. The display substrate according to claim 6 , further comprising:
a first insulation layer between the second electrode plate of the first compensation capacitor and the gate electrode;
a second insulation layer between the gate electrode and the first electrode plate of the first compensation capacitor; and
a third insulation layer between the first electrode plate of the first compensation capacitor and the second electrode plate of the second compensation capacitor, wherein
the first part of second sub-routing line is electrically connected with the second electrode plate of the first compensation capacitor through a first via hole which penetrates through the first insulation layer, the second insulation layer, and the third insulation layer and exposes the second electrode plate of the first compensation capacitor.

8. The display substrate according to claim 6 , wherein the first part of second sub-routing line is integrated with the second electrode plate of the second compensation capacitor.

9. The display substrate according to claim 6 , further comprising:
a plurality of second signal lines configured to provide a second display signal to the plurality of sub-pixels, wherein the first part of second signal line of the plurality of second signal lines passes through the inter-opening region and the first dummy sub-pixel along the second direction, and the first part of second signal line of the plurality of second signal lines is at a side of the second electrode plate of the second compensation capacitor away from the base substrate;
the first portion of the second electrode plate of the second c

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Zhang Xin
• Zhou Yang
• Dai Junxiu
• Liao Maoying
• Zhang Yi
• Shu Xiaoqing
• Ma Hongwei
• Du Mengmeng
• Wang Rong
• Dong Xiangdan
• Zhang Zhenhua
• Yang Shuangbin
• Cheng Bo
• Li Yujing

Classifications

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/88

  Dummy elements, i.e. elements having non-functional features · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title