Allocation of shared reserve memory

US12192122B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12192122-B2
Application numberUS-202418581423-A
CountryUS
Kind codeB2
Filing dateFeb 20, 2024
Priority dateJan 31, 2022
Publication dateJan 7, 2025
Grant dateJan 7, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A device includes ports, a packet processor, and a memory management circuit. The ports communicate packets over a network. The packet processor processes the packets using queues. The memory management circuit maintains a shared buffer in a memory and adaptively allocates memory resources from the shared buffer to the queues, maintains in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by the queues, identifies, among the queues, a queue that requires additional memory resources, the queue having an occupancy that is (i) above a current value of a dynamic threshold, rendering the queue ineligible for additional allocation from the shared buffer, and (ii) no more than a defined margin above the current value of the dynamic threshold, rendering the queue eligible for allocation from the shared-reserve memory pool, and allocates memory resources to the identified queue from the shared-reserve memory pool.

First claim

Opening claim text (preview).

The invention claimed is: 1. A device, comprising: one or more ports, to communicate packets over a network; a packet processor, to process the packets using a plurality of queues; and a memory management circuit, to: maintain a shared buffer in a memory, and adaptively allocate memory resources from the shared buffer to the queues; maintain in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by one or more of the queues; identify, among the queues, a queue that requires additional memory resources, the queue having an occupancy that is: (i) above a current value of a dynamic threshold, rendering the queue ineligible for additional allocation from the shared buffer, and (ii) no more than a defined margin above the current value of the dynamic threshold, rendering the queue eligible for allocation from the shared-reserve memory pool; and allocate memory resources to the identified queue from the shared-reserve memory pool. 2. The device according to claim 1 , wherein the memory management circuit is to identify that the queue requires additional memory resources by receiving a request from the queue. 3. The device according to claim 1 , wherein the memory management circuit is to pre-allocate to the queue a private-reserve memory resource, irrespective of the shared buffer and the shared-reserve memory pool. 4. The device according to claim 1 , wherein the queues are associated with a same port of the network device. 5. A memory management circuit, comprising: one or more interfaces, to communicate with a plurality of queues of the network device that process packets, and with a memory; and circuitry, to: maintain a shared buffer in the memory, and adaptively allocate memory resources from the shared buffer to the queues; maintain in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by one or more of the queues; identify, among the queues, a queue that requires additional memory resources, the queue having an occupancy that is: (i) above a current value of a dynamic threshold, rendering the queue ineligible for additional allocation from the shared buffer, and (ii) no more than a defined margin above the current value of the dynamic threshold, rendering the queue eligible for allocation from the shared-reserve memory pool; and allocate memory resources to the identified queue from the shared-reserve memory pool. 6. The memory management circuit according to claim 5 , wherein the circuitry is to identify that the queue requires additional memory resources by receiving a request from the queue. 7. The memory management circuit according to claim 5 , wherein the circuitry is to pre-allocate to the queue a private-reserve memory resource, irrespective of the shared buffer and the shared-reserve memory pool. 8. The memory management circuit according to claim 5 , wherein the queues are associated with a same port of the network device. 9. A method for communication, the method comprising: communicating packets over a network, and processing the packets using a plurality of queues; maintaining a shared buffer in a memory, and adaptively allocating memory resources from the shared buffer to the queues; maintaining in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by one or more of the queues; identifying, among the queues, a queue that requires additional memory resources, the queue having an occupancy that is: (i) above a current value of a dynamic threshold, rendering the queue ineligible for additional allocation from the shared buffer, and (ii) no more than a defined margin above the current value of the dynamic threshold, rendering the queue eligible for allocation from the shared-reserve memory pool; and allocating memory resources to the identified queue from the shared-reserve memory pool. 10. The method according to claim 9 , wherein identifying that the queue requires additional memory resources comprises receiving a request from the queue. 11. The method according to claim 9 , wherein further comprising pre-allocate to the queue a private-reserve memory resource, irrespective of the shared buffer and the shared-reserve memory pool. 12. The method according to claim 9 , wherein the queues in the subset are associated with a same port of the network device. 13. A method for memory management, the method comprising: communicating with a plurality of queues of the network device that process packets, and with a memory; maintaining a shared buffer in the memory, and adaptively allocating memory resources from the shared buffer to the queues; maintaining in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by one or more of the queues; identifying, among the queues, a queue that requires additional memory resources, the queue having an occupancy that is: (i) above a current value of a dynamic threshold, rendering the queue ineligible for additional allocation from the shared buffer, and (ii) no more than a defined margin above the current value of the dynamic threshold, rendering the queue eligible for allocation from the shared-reserve memory pool; and allocating memory resources to the identified queue from the shared-reserve memory pool. 14. A method for memory management using queues, the method comprising: maintaining in a memory (i) a shared buffer and (ii) a shared-reserve memory pool; identifying a queue that requires additional memory resources and has an occupancy that is: (i) above a current value of a dynamic threshold, rendering the queue ineligible for additional allocation from the shared buffer, and (ii) no more than a defined margin above the current value of the dynamic threshold, rendering the queue eligible for allocation from the shared-reserve memory pool; and allocating memory resources to the identified queue from the shared-reserve memory pool.

Assignees

Inventors

Classifications

  • including multiple buffers, e.g. buffer pools · CPC title

  • using dynamic buffer space allocation · CPC title

  • in combination with information about buffer occupancy at either end or at transit nodes · CPC title

  • by minimising distances, e.g. by selecting a route with minimum of number of hops · CPC title

  • Queue scheduling · CPC title

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Frequently asked questions

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What does patent US12192122B2 cover?
A device includes ports, a packet processor, and a memory management circuit. The ports communicate packets over a network. The packet processor processes the packets using queues. The memory management circuit maintains a shared buffer in a memory and adaptively allocates memory resources from the shared buffer to the queues, maintains in the memory, in addition to the shared buffer, a shared-…
Who is the assignee on this patent?
Mellanox Technologies Ltd
What technology area does this patent fall under?
Primary CPC classification H04L49/103. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 07 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).