Intermediate logical interfaces in a virtual distributed router environment

US12192103B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12192103-B2
Application numberUS-202318241234-A
CountryUS
Kind codeB2
Filing dateSep 1, 2023
Priority dateJun 30, 2015
Publication dateJan 7, 2025
Grant dateJan 7, 2025

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A LRE (logical routing element) that have LIFs that are active in all host machines spanned by the LRE as well as LIFs that are active in only a subset of those spanned host machines is provided. A host machine having an active LIF for a particular L2 segment would perform the L3 routing operations for network traffic related to that L2 segment. A host machine having an inactive LIF for the particular L2 segment would not perform L3 routing operations for the network traffic of the L2 segment.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forwarding packets from a logical network to an external network through an edge gateway, the method comprising: at a first host computer: receiving a packet at a first router that executes on the first host computer to implement a logical router for the logical network along with a plurality of other routers executing on a plurality of other host computers; performing a routing lookup to determine that the packet is directed to an interface that is not active on the first host computer but is active on a second host computer on which the edge gateway executes; using a logical switch implemented by the first and second host computers to forward the packet to the second host computer for the packet to be processed by the gateway and forwarded to the external network. 2. The method of claim 1 , wherein the interface is a logical interface (LIF). 3. The method of claim 2 , wherein the LIF is only active on any host computer that executes an edge gateway connecting the logical network to another network. 4. The method of claim 2 , wherein the LIF is associated with the logical router. 5. The method of claim 4 , wherein the packet is a first packet and the interface is a first interface, the method further comprising: at a first host computer: receiving a second packet at the first router; performing a routing lookup to determine that the packet is directed to a second interface that is active on the first host computer; forwarding the second packet through the second interface to reach a destination of the second packet in the logical network. 6. The method of claim 5 further comprising: identifying a layer 2 (L2) destination address for second packet by using the destination IP address of the second packet; providing the second packet with the identified L2 destination address to a switch to forward the packet to the second packet's destination in the logical network. 7. The method of claim 1 further comprising assigning to the packet a media access control (MAC) address that is used to identify the interface of the logical switch on the second hot computer. 8. The method of claim 7 , wherein the MAC is an rMAC when the only edge gateway is the edge gateway executing on the second host computer or is an IMAC associated with the second host computer when more than one edge gateways execute on more than one host computers. 9. The method of claim 1 , wherein the external network is a virtual local area network (VLAN). 10. The method of claim 9 , wherein the logical network is an overlay logical network that is established by encapsulating packets sent between the host computers with encapsulation headers that store overlay logical network data. 11. A non-transitory machine readable medium storing a program for execution by at least one processing unit of a first host computer to forward packets from a logical network to an external network through an edge gateway, the program comprising sets of instructions for: receiving a packet at a first router that executes on the first host computer to implement a logical router for the logical network along with a plurality of other routers executing on a plurality of other host computers; performing a routing lookup to determine that the packet is directed to an interface that is not active on the first host computer but is active on a second host computer on which the edge gateway executes; using a logical switch implemented by the first and second host computers to forward the packet to the second host computer for the packet to be processed by the gateway and forwarded to the external network. 12. The non-transitory machine readable medium of claim 11 , wherein the interface is a logical interface (LIF). 13. The non-transitory machine readable medium of claim 12 , wherein the LIF is only active on any host computer that executes an edge gateway connecting the logical network to another network. 14. The non-transitory machine readable medium of claim 12 , wherein the LIF is associated with the logical router. 15. The non-transitory machine readable medium of claim 14 , wherein the packet is a first packet and the interface is a first interface, the program further comprising sets of instructions for: receiving a second packet at the first router; performing a routing lookup to determine that the packet is directed to a second interface that is active on the first host computer; forwarding the second packet through the second interface to reach a destination of the second packet in the logical network. 16. The non-transitory machine readable medium of claim 15 , wherein the program further comprises sets of instructions for: identifying a layer 2 (L2) destination address for second packet by using the destination IP address of the second packet; providing the second packet with the identified L2 destination address to a switch to forward the packet to the second packet's destination in the logical network. 17. The non-transitory machine readable medium of claim 11 , wherein the program further comprises a set of instructions for assigning to the packet a media access control (MAC) address that is used to identify the interface of the logical switch on the second hot computer. 18. The non-transitory machine readable medium of claim 17 , wherein the MAC is an rMAC when the only edge gateway is the edge gateway executing on the second host computer or is an IMAC associated with the second host computer when more than one edge gateways execute on more than one host computers. 19. The non-transitory machine readable medium of claim 11 , wherein the external network is a virtual local area network (VLAN). 20. The non-transitory machine readable medium of claim 19 , wherein the logical network is an overlay logical network that is established by encapsulating packets sent between the host computers with encapsulation headers that store overlay logical network data.

Assignees

Inventors

Classifications

  • Distributed routing · CPC title

  • Assignment of logical groups to network elements · CPC title

  • in the network layer [OSI layer 3], e.g. X.25 (H04L69/16 takes precedence) · CPC title

  • using forward notification · CPC title

  • H04L45/586Primary

    of virtual routers · CPC title

Patent family

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Frequently asked questions

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What does patent US12192103B2 cover?
A LRE (logical routing element) that have LIFs that are active in all host machines spanned by the LRE as well as LIFs that are active in only a subset of those spanned host machines is provided. A host machine having an active LIF for a particular L2 segment would perform the L3 routing operations for network traffic related to that L2 segment. A host machine having an inactive LIF for the par…
Who is the assignee on this patent?
Nicira Inc
What technology area does this patent fall under?
Primary CPC classification H04L45/586. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 07 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).