Shared memory

Patent metadata

Field	Value
Publication number	US-12192024-B2
Application number	US-202017103711-A
Country	US
Kind code	B2
Filing date	Nov 24, 2020
Priority date	Nov 18, 2020
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

Examples described herein includes a network interface controller comprising a memory interface and a network interface, the network interface controller configurable to provide access to local memory and remote memory to a requester, wherein the network interface controller is configured with an amount of memory of different memory access speeds for allocation to one or more requesters. In some examples, the network interface controller is to grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for different memory access speeds for allocation to the requester. In some examples, the network interface controller is to grant or deny a memory access request from a requester based on a configuration of memory allocated to the requester. In some examples, the network interface controller is to regulate quality of service of memory access requests from requesters.

First claim

What is claimed is:

1. An apparatus comprising:
a network interface controller comprising a direct memory access (DMA) circuitry, a memory interface, and a network interface, the network interface controller configurable to provide access to a first memory and a second memory, wherein:
the network interface controller is configured with amounts of memory in the first memory and the second memory associated with different memory access speeds for allocation to one or more requesters based on class of service of the one or more requesters,
a first amount of memory in the first memory is associated with a first class of service and first memory access speed,
a second amount of memory in the second memory is associated with a second class of service and second memory access speed,
the first class of service is higher than the second class of service,
the first memory access speed is higher than the second memory access speed,
the network interface controller is to access the first memory using the memory interface, and
the network interface controller is to access the second memory by transmission or receipt of Ethernet packets.

2. The apparatus of claim 1 , wherein the network interface controller is to grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for one or more of the different memory access speeds for allocation to the requester.

3. The apparatus of claim 1 , wherein the network interface controller is to grant or deny a memory access request from a requester based on a configuration of memory allocated to the requester.

4. The apparatus of claim 1 , wherein the network interface controller is to regulate quality of service (QOS) of memory access requests from the one or more requesters.

5. The apparatus of claim 1 , wherein the first memory comprises a lower latency memory technology than that of the second memory.

6. The apparatus of claim 1 , wherein the first memory comprises a memory connected to the network interface controller using the memory interface.

7. The apparatus of claim 1 , wherein the second memory comprises a memory device connected to the network interface controller using a fabric or network.

8. The apparatus of claim 1 , wherein the network interface controller is permitted to configure memory allocation to the one or more requesters within a trust group and deny memory allocation to a requester outside of the trust group.

9. The apparatus of claim 1 , comprising one or more of a server, rack, or data center and wherein the one or more of a server, rack, or data center is coupled to the network interface controller and the one or more of a server, rack, or data center is to execute a requester of the one or more requesters to request allocation of an amount of memory in the first memory and/or the second memory.

10. The apparatus of claim 1 , wherein:
a first memory address range is associated a first latency level,
a second memory address range is associated a second latency level,
the second latency level is higher than the first latency level, and
the first memory address range is different than the second memory address range.

11. At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
enable or disable a network interface device to:
manage access to a first memory and a second memory granted to a requester, wherein
the network interface device is configured with amounts of memory in the first memory and the second memory associated with different memory access speeds for allocation to one or more requesters based on class of service of the one or more requesters,
the network interface device comprises a direct memory access (DMA) circuitry, a memory interface, and network interface,
a first amount of memory in the first memory is associated with a first class of service and first memory access speed,
a second amount of memory in the second memory is associated with a second class of service and second memory access speed,
the first class of service is higher than the second class of service,
the first memory access speed is higher than the second memory access speed,
the network interface device is to access the first memory using the memory interface, and
the network interface device is to access the second memory by transmission or receipt of Ethernet packets.

12. The computer-readable medium of claim 11 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for different memory access speeds for allocation to the requester.

13. The computer-readable medium of claim 11 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
enable or disable the network interface device to regulate quality of service (QOS) of memory access requests from the one or more requesters.

14. The computer-readable medium of claim 11 , wherein:
the first memory comprises a local memory connected to the network interface device using a memory interface and
the second memory comprises a memory connected to the network interface device using a fabric or network.

15. A method comprising:
a network interface device providing access to a first memory and a second memory to one or more requesters, based on configured amounts of memory of different memory access speeds allocated to one or more requesters based on class of service of the one or more requesters, wherein:
the network interface device comprises a direct memory access (DMA) circuitry, a memory interface, and network interface,
a first amount of memory in the first memory is associated with a first class of service and first memory access speed,
a second amount of memory in the second memory is associated with a second class of service and second memory access speed,
the first class of service is higher than the second class of service,
the first memory access speed is higher than the second memory access speed,
the network interface device accesses the first memory using the memory interface, and
the network interface device accesses the second memory by transmission or receipt of Ethernet packets.

16. The method of claim 15 , comprising:
granting or denying, by the network interface device, a memory allocation request from a requester of the one or more requesters based on a configuration of an amount of memory for one or more of the different memory access speeds for allocation to the requester.

17. The method of claim 15 , comprising:
granting or denying, by the network interface device, a memory access request from a requester of the one or more requesters based on a configuration of memory allocated to the requester.

18. The method of claim 15 , comprising:
regulating quality of service of memory access requests from the one or more requesters.

19. The method of claim 15 , wherein the first memory comprises a lower latency memory technology than that of the second memory.

20. The method of claim 15 , wherein the second memory comprises a memory connected to the network interface device using a fabric or network.

Assignees

• Intel Corp

Inventors

• Coury Bassam N
• Sen Sujoy
• Willis Thomas E
• Srivastava Durgesh

Classifications

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F12/0862

  with prefetch · CPC title

• H04L45/74

  Address processing for routing · CPC title

• G06F13/4059

  where the synchronisation uses buffers, e.g. for speed matching between buses · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title