One-dimensional hard-input FEC receiver for digital communication

Patent metadata

Field	Value
Publication number	US-12191995-B2
Application number	US-202217861140-A
Country	US
Kind code	B2
Filing date	Jul 8, 2022
Priority date	Jul 8, 2022
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

A digital receiver based on one-dimensional hard demapping of an input symbol stream (FEC encoded) is configured to utilize LLRs created to have bit-specific magnitude values to improve the probability that the included decoder (such as an LDPC decoder) properly recovers each bit from the original stream. The digital receiver may be used with various types of data modulation schemes (e.g., PAM3, PAM4, DSQ8, etc.), with a specific set of LLR magnitudes created for each modulation scheme.

First claim

What is claimed is:

1. A digital receiver for recovering data from a FEC-encoded signal having a stream of N bits mapped into M transmitted symbols, comprising
a one-dimensional hard demapper for generating a set of K demapped bits for each arriving symbol, where K=ceil(N/M); and
a FEC decoder for producing a stream of decoded data bits from the output of the one-dimensional hard demapper, the FEC decoder including
an apparatus responsive to a set of M*K demapped bits including at least a most-significant bit (MSB) and a least-significant bit (LSB), the apparatus configured to convert the set of M*K demapped bits into a plurality of N log-likelihood ratios (LLRs) associated with the stream of N bits in a one-to-one relationship, the apparatus comprising
at least one processor, and
at least one memory including computer program code, wherein the at least one memory and the computer program code are configured, with the at least one processor, to cause the apparatus to generate the plurality of N LLRs, each LLR defined by a magnitude and a sign, the magnitude selected from a plurality of predefined, different LLR magnitudes based on at least probability characteristics associated within a bit-specific ordering within the set of M*K demapped bits from the MSB to the LSB, the magnitude of the MSB being greater than at least the magnitude of the LSB; and

a decoding engine responsive to the LLRs generated by the apparatus and producing therefrom an output stream of decoded data bits.

2. The digital receiver as defined in claim 1 wherein the decoding engine comprises an LDPC decoder.

3. The digital receiver as defined in claim 1 wherein the decoding engine performs one or more iterations to produce the output stream, including a step of updating LLR magnitudes for at least some of the iterations.

4. The digital receiver as defined in claim 1 wherein the decoding engine performs one or more iterations to produce the output stream, each iteration using as an input the plurality of N LLRs generated by the apparatus.

5. The digital receiver as defined in claim 1 wherein the mapping is such that the quantity N/M defines an integer value.

6. The digital receiver as defined in claim 5 wherein the mapping comprises a PAM4 scheme, with N=2 and M=1, the one-dimensional hard demapper generating a set of K=2 demapped bits b n , defined as a (MSB, LSB) pair.

7. The digital receiver as defined in claim 6 , wherein the at least one memory stores a set of at least two LLR magnitudes A and B, with A>B, and wherein the at least one processor and the at least one memory including computer program code are configured, to cause the apparatus to at least select LLR magnitude values (|LLR init |) from the applied K demapped bits b n based upon the following:
if b n is MSB,|LLR init |=|A|⇒LLR n =−1 b n |A|;

if b n is LSB,|LLR init |=|B|⇒LLR n =−1 b n |B|.

8. The digital receiver as defined in claim 6 , wherein the at least memory stores a set of at least three LLR magnitudes A 1 , A 2 , and A 3 , where A 1 >A 2 >A 3 , and wherein the at least one memory including computer program code are configured, with the at least one processor, to cause the apparatus to at least generate N LLR magnitude values from the applied K demapped bits b n based upon the following:
if b n is MSB and LSB= 0,| LLR init |=|A 1|, and LLR n =−1 b n |A 1|;

if b n is MSB and LSB= 1,| LLR init |=|A 2|, and LLR n =−1 b n |A 2|; and

if b n is LSB,|LLR init |=|A 3|, and LLR n =−1 b n |A 3|.

9. The digital receiver as defined in claim 1 wherein characteristics of a communication channel used to transmit the M symbols are used in combination with the bit-specific ordering by the at least one processor and the at least one memory including computer program code to select LLR magnitudes from the plurality of predefined, different LLR magnitudes.

10. The digital receiver as defined in claim 9 wherein an additive white Gaussian noise (AWGN) model of the communication channel is used in the creation of the plurality of predefined, different LLR magnitudes.

11. The digital receiver as defined in claim 9 wherein a set of histograms measured along the communication channel is used in the creation of the plurality of predefined, different LLR magnitudes.

12. The digital receiver as defined in claim 1 wherein the mapping is such that the quantity N/M defines a non-integer value.

13. The digital receiver as defined in claim 12 wherein the mapping comprises a scheme using N=3 and M=2, the one-dimensional hard demapper generating a set of K=ceil (N/M)=2 demapped bits for each symbol, and the apparatus of the FEC decoder using K*M=4 demapped bits to generate the plurality of N LLRs.

14. The digital receiver as defined in claim 13 wherein the mapping scheme is selected from a group consisting of PAM3 mapping and DSQ8 mapping.

15. The digital received as defined in claim 12 wherein the plurality of predefined, different LLR magnitudes includes a magnitude value of “zero”.

16. The digital receiver as defined in claim 12 wherein the combination of the at least one processor and at least one memory including computer program code causes the apparatus to generate the plurality of N LLRs by evaluating a selected demapped region of a two-dimensional constellation and determining a most likely constellation point from which any samples in the selected demapped region originate.

17. The digital receiver as defined in claim 1 wherein the digital receiver is configured as a downstream receiver within an optical network unit (ONU) for receiving an incoming optical data stream from an associated optical line terminal (OLT), where the ONU and OLT are associated with a passive optical network (PON).

18. The digital receiver as defined in claim 1 wherein the digital receiver is configured as an upstream receiver within an optical line terminal (OLT) for receiving an incoming optical data stream from an associated optical network unit (ONU), where the OLT and ONU are associated with a passive optical network (PON).

Assignees

• Nokia Solutions & Networks Oy

Inventors

• Lefevre Yannick
• Mahadevan Amitkumar
• Verplaetse Michiel

Classifications

• H04L1/0061

  Error detection codes · CPC title

• H04B10/27

  Arrangements for networking · CPC title

• H04B10/69

  Electrical arrangements in the receiver · CPC title

• H03M13/255

  with Low Density Parity Check [LDPC] codes · CPC title

• H03M13/1111

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title