Local oscillator (LO) generation for carrier aggregation in phased array front ends

Patent metadata

Field	Value
Publication number	US-12191897-B2
Application number	US-202418401893-A
Country	US
Kind code	B2
Filing date	Jan 2, 2024
Priority date	Aug 26, 2019
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

First claim

What is claimed is:

1. A local oscillator (LO) signal generator, comprising:
a frequency synthesizer configured to generate a first reference signal having a first frequency;
a digital to time converter (DTC) configured to generate a second reference signal based upon the first reference signal, the second reference signal having a second frequency that is a fractional multiple of the first frequency;
a high-band (HB) path including a HB injection locked frequency multiplier (ILFM), the HB ILFM configured to generate one or more HB local oscillator (LO) signals having a HB LO frequency that is based upon the first frequency associated with the first reference signal; and
a low-band (LB) frequency path including a LB ILFM, the LB ILFM configured to generate one or more LB local oscillator (LO) signals having a LB LO frequency that is based upon the second frequency associated with the second reference signal.

2. The LO signal generator of claim 1 , wherein the HB ILFM is from among a plurality of HB ILFMs within the HB path, each one of the plurality of HB ILFMs being associated with a respective transceiver chain, and
wherein the LB ILFM is from among a plurality of LB ILFMs within the LB path, each one of the plurality of LB ILFMs being associated with a respective transceiver chain.

3. The LO signal generator of claim 1 , wherein the HB ILFM is configured to generate a set of quadrature LO signals as the one or more HB LO signals, and
wherein the LB ILFM is configured to generate a set of quadrature LO signals as the one or more LB LO signals.

4. The LO signal generator of claim 1 , wherein the HB ILFM is coupled to one or more mixers configured to perform direct downconversion of received signals to baseband using the one or more HB LO signals, and
wherein the LB ILFM is coupled to one or more mixers configured to perform direct downconversion of received signals to baseband using the one or more LB LO signals.

5. The LO signal generator of claim 4 , wherein the received signals that are directly downconverted to baseband via the one or more mixers in the HB path and the received signals that are directly downconverted to baseband via the one or more mixers in the LB path are within a range of mm-wave frequencies.

6. The LO signal generator of claim 1 , wherein the HB ILFM is configured to generate the one or more HB LO signals having the HB LO frequency that is an integer multiple of the first frequency associated with the first reference signal.

7. The LO signal generator of claim 1 , further comprising:
a further DTC configured to generate, from the first reference signal, a fractionally-multiplied first reference signal having a frequency that is a fractional multiple of the first frequency,
wherein the HB ILFM is configured to generate the one or more HB LO signals having the HB LO frequency that is an integer multiple of the fractional multiple of the first frequency associated with the fractionally-multiplied first reference signal.

8. The LO signal generator of claim 1 , further comprising:
frequency divider circuitry configured to perform frequency division on the first reference signal to generate a frequency-divided reference signal, and
wherein the DTC is further configured to perform a fractional multiplication of the frequency-divided reference signal to generate the second reference signal.

9. The LO signal generator of claim 1 , wherein the DTC is configured to receive digital phase ramp data that is varied to adjust the fractional multiple of the first frequency to thereby adjust the second frequency associated with the second reference signal.

10. A wireless device, comprising:
a plurality of transceiver chains;
processing circuitry; and
a memory configured to store executable instructions that, when executed by the processing circuitry, causes each transceiver chain from the plurality of transceiver chains to:
generate a first reference signal having a first frequency;
generate, via a digital to time converter (DTC), a second reference signal based upon the first reference signal, the second reference signal having a second frequency that is a fractional multiple of the first frequency;
generate, via a high-band (HB) injection locked frequency multiplier (ILFM), one or more HB local oscillator (LO) signals having a HB LO frequency that is based upon the first frequency associated with the first reference signal; and
generate, via a low-band (LB) ILFM, one or more LB local oscillator (LO) signals having a LB LO frequency that is based upon the second frequency associated with the second reference signal.

11. The wireless device of claim 10 , wherein the HB ILFM is configured to generate a set of quadrature LO signals as the one or more HB LO signals, and
wherein the LB ILFM is configured to generate a set of quadrature LO signals as the one or more LB LO signals.

12. The wireless device of claim 10 , wherein the memory is further configured to store executable instructions that, when executed by the processing circuitry, causes each transceiver chain from the plurality of transceiver chains to:
generate, via another DTC from the first reference signal, a fractionally-multiplied first reference signal having a frequency that is a fractional multiple of the first frequency, and
generate, via the HB ILFM, the one or more HB LO signals having the HB LO frequency that is an integer multiple of the fractional multiple of the first frequency associated with the fractionally-multiplied first reference signal.

Assignees

• Intel Corp

Inventors

• Ravi Ashoke
• Jann Benjamin
• Patnaik Satwik

Classifications

• H03L7/0816

  the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input · CPC title

• H01Q3/40

  with phasing matrix · CPC title

• G01R27/06

  Measuring reflection coefficients; Measuring standing-wave ratio · CPC title

• H03L7/24

  using a reference signal directly applied to the generator · CPC title

• H04B1/0483 Primary

  Transmitters with multiple parallel paths · CPC title