Nonvolatile memory device preventing overshoot of internal voltage and method of operating nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-12190964-B2
Application number	US-202217750315-A
Country	US
Kind code	B2
Filing date	May 21, 2022
Priority date	Nov 8, 2021
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

In a method of operating a nonvolatile memory device that includes a memory block including cell strings where each of the cell strings includes a string selection transistor, memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction, each of word-lines coupled to the memory cells is set up to a respective target level during a word-line set-up period, a sensing operation on target memory cells is performed by applying a read voltage to a selected word-line coupled to the target memory cells while applying a read pass voltage to unselected word-lines during a sensing period, and while consuming an internal voltage connected to the unselected word-lines in a particular circuit in the nonvolatile memory device, a voltage level of the unselected word-lines is recovered to a level of the internal voltage during a discharge period of a word-line recovery period.

First claim

What is claimed is:

1. A method of operating a nonvolatile memory device that includes at least one memory block including a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a bit-line and a common source line, the method comprising:
during a word-line setup period, setting up each of a plurality of word-lines coupled to the plurality of memory cells to a respective target level;
during a sensing period, performing a sensing operation on target memory cells of the plurality of memory cells by applying a read voltage to a selected word-line coupled to the target memory cells, among the plurality of word-lines while applying a read pass voltage to unselected word-lines among the plurality of word-lines;
during a word-line recovery period, performing a word-line recovery operation by recovering a voltage level of the read pass voltage applied to the unselected word-lines to a level of an internal voltage; and
during a discharge period within the word-line recovery period, consuming the internal voltage connected to the unselected word-lines by activating a particular circuit of the nonvolatile memory device,
wherein the particular circuit is supplied with the internal voltage and is not associated with the word-line recovery operation.

2. The method of claim 1 , wherein the consuming of the internal voltage includes:
during the discharge period, turning on and turning off transistors of the particular circuit, repeatedly,
wherein the performing of the sensing operation includes sensing and latching data of the target memory cells by a selected page buffer among a plurality of page buffers of a page buffer circuit in the nonvolatile memory device, and
wherein the particular circuit includes the plurality of page buffers coupled to the at least one memory block through a plurality of bit-lines.

3. The method of claim 1 , wherein the consuming of the internal voltage includes:
during the discharge period, generating a toggling clock signal based on the internal voltage from the particular circuit,
wherein the performing of the sensing operation includes generating word-line voltages including the read voltage and the read pass voltage from a voltage generation circuit in the nonvolatile memory device, and
wherein the particular circuit includes an oscillator of the voltage generation circuit configured to generate the toggling clock signal.

4. The method of claim 1 , wherein the consuming of the internal voltage includes:
during the discharge period, generating a dummy voltage based on the internal voltage from the particular circuit,
wherein the performing of the sensing operation includes generating word-line voltages including the read voltage, the read pass voltage, and the dummy voltage from a voltage generation circuit in the nonvolatile memory device, and
wherein the particular circuit includes a dummy voltage generator of the voltage generation circuit and is configured to generate the dummy voltage.

5. The method of claim 1 , wherein the discharge period is determined based on comparing a level of the internal voltage and a reference voltage.

6. The method of claim 1 , wherein the discharge period is pre-determined by a control circuit configured to control an operation of the nonvolatile memory device.

7. The method of claim 1 , wherein a starting time point and an ending time point of the discharge period are variable.

8. A nonvolatile memory device comprising:
a memory cell array that includes at least one memory block including a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a bit-line and a common source line; and
a control circuit configured to:
during a word-line set-up period, set up each of a plurality of word-lines coupled to the plurality of memory cells to a respective target level;
during a sensing period, perform a sensing operation on target memory cells of the plurality of memory cells by applying a read voltage to a selected word-line coupled to the target memory cells, among the plurality of word-lines while applying a read pass voltage to unselected word-lines among the plurality of word-lines;
during a word-line recovery period, perform a word-line recovery operation by recovering a voltage level of the unselected word-lines to a level of an internal voltage; and
during a discharge period within the word-line recovery period, consume the internal voltage connected to the unselected word-lines to which the read pass voltage is applied, in a particular circuit of the nonvolatile memory device,
wherein the particular circuit supplied with the internal voltage is configured to be activated during the discharge period, and the particular circuit is not associated with the word-line recovery operation.

9. The nonvolatile memory device of claim 8 , further comprising:
a voltage generation circuit configured to generate word-line voltages including the read voltage and the read pass voltage based on control signals from the control circuit;
an address decoder configured to provide the word-line voltages to the at least one memory block based on a row address; and
a page buffer circuit coupled to the at least one memory block through a plurality of bit-lines, the page buffer circuit configured to latch sensed data in the sensing operation.

10. The nonvolatile memory device of claim 9 , wherein the particular circuit includes a plurality of page buffers of the page buffer circuit, and
wherein the control circuit is configured to consume the internal voltage by turning on and turning off transistors using the internal voltage, repeatedly, in each of the plurality of page buffers during the discharge period.

11. The nonvolatile memory device of claim 10 , wherein the transistors of the page buffer circuit are configured to activate transistors d-that connect each sensing node of each of the plurality of page buffers to latches of each of the plurality of page buffers.

12. The nonvolatile memory device of claim 9 , wherein the particular circuit includes an oscillator of the voltage generation circuit, and
wherein the control circuit is configured to control the voltage generation circuit to generate a toggling clock signal based on the internal voltage from the oscillator during the discharge period.

13. The nonvolatile memory device of claim 12 , wherein the control circuit is configured to consuming the internal voltage by enabling the oscillator during the discharge period.

14. The nonvolatile memory device of claim 9 , wherein:
the particular circuit includes a dummy voltage generator of the voltage generation circuit,
the control circuit is configured to, during the discharge period, control the dummy voltage generator to generate a dummy voltage based on the internal voltage, and
the control circuit is configured to consume the internal voltage by enabling the dummy voltage generator during the discharge period.

15. The nonvolatile memory device of claim 9 , further comprising:
an overshoot detector configured to compare the internal voltage with a reference voltage to generate an overshoot detection flag based on a result of the comparison,
wherein the control circuit is configured to set the discharge period based on the overshoot detection flag.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Sanggi
• Kim Chaehoon
• Park Sangwon
• Cho Jiho

Classifications

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title