Audio stack power control based on latency

US12190012B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12190012-B2
Application numberUS-202117482070-A
CountryUS
Kind codeB2
Filing dateSep 22, 2021
Priority dateSep 22, 2021
Publication dateJan 7, 2025
Grant dateJan 7, 2025

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Example apparatus disclosed herein compare one or more audio latency characteristics with one or more audio latency requirements in response to detection of an audio silence event, the audio latency characteristic(s) associated with at least one of a hardware layer or a device layer of an audio stack of a compute device, the audio latency requirement(s) associated with an application. Disclosed example apparatus also control a device layer of the audio stack to enter a device layer low power mode in response to a first determination that the audio latency requirement(s) is/are met by the audio latency characteristic(s). Disclosed example apparatus further control a hardware layer of the audio stack to enter a hardware layer low power mode in response to the first determination and a second determination that an operation condition for entry into the hardware layer low power mode is met.

First claim

Opening claim text (preview).

What is claimed is: 1. A compute device to perform audio stack power control, the compute device comprising: interface circuitry to interface with an audio device, the audio device including at least one of an amplifier or an equalizer; digital signal processor circuitry to perform one or more audio processing operations associated with the audio device; instructions; and at least one processor circuit to be programmed by the instructions to at least: detect an audio silence event; compare a first audio latency characteristic and a second audio latency characteristic with one or more audio latency requirements after detection of the audio silence event, the first audio latency characteristic associated with a first low power mode supported by the audio device, the first low power mode to cause the at least one of the amplifier or the equalizer of the audio device to be turned off, the second audio latency characteristic associated with a second low power mode supported by the digital signal processor circuitry of the compute device, the second low power mode to cause the digital signal processor circuitry to enter low power operation, the one or more audio latency requirements associated with an application on the compute device; control the audio device to enter the first low power mode after a determination that the one or more audio latency requirements are met by the first audio latency characteristic; and control the digital signal processor circuitry to enter the second low power mode after a determination that the one or more audio latency requirements are met by the second audio latency characteristic. 2. The compute device of claim 1 , wherein one or more of the at least one processor circuit is to: compare a third audio latency characteristic with the one or more audio latency requirements after the detection of the audio silence event, the third audio latency characteristic associated with a software layer of the compute device; and control the software layer of the compute device to stop an audio stream associated with the audio silence event after a determination that the one or more audio latency requirements are met by the third audio latency characteristic. 3. The compute device of claim 1 , wherein the audio silence event corresponds to a playback silence event, the audio device is an audio playback device, and one or more of the at least one processor circuit is to: control the digital signal processor circuitry to enter the second low power mode after the determination that the one or more audio latency requirements are met by the second audio latency characteristic and a determination that an operation condition is met, the operation condition to be met when a reference audio stream is not required by the application. 4. The compute device of claim 3 , wherein one or more of the at least one processor circuit is to: cause generation of fabricated audio data to include in the reference audio stream when the reference audio stream is required by the application. 5. The compute device of claim 1 , wherein the audio silence event corresponds to a capture silence event, the audio device is an audio capture device, and one or more of the at least one processor circuit is to: control the digital signal processor circuitry to enter the second low power mode after the determination that the one or more audio latency requirements are met by the second audio latency characteristic and a determination that an operation condition is met, the operation condition to be met when a reference audio stream is not required by the application. 6. The compute device of claim 5 , wherein one or more of the at least one processor circuit is to: cause generation of fabricated audio data to include in the reference audio stream when the reference audio stream is required by the application. 7. The compute device of claim 1 , wherein one or more of the at least one processor circuit is to: detect an audio activity event after the audio device has entered the first low power mode and the digital signal processor circuitry has entered the second low power mode; and after detection of the audio activity event, (i) control the audio device to exit the first low power mode and (ii) control the digital signal processor circuitry to exit the second low power mode. 8. The compute device of claim 7 , wherein the audio activity event corresponds to an interrupt generated by the audio device. 9. At least one non-transitory computer readable medium comprising computer readable instructions to cause at least one processor circuit of a compute device to at least: detect an audio silence event; compare a first audio latency characteristic and a second audio latency characteristic with one or more audio latency requirements after detection of the audio silence event, the first audio latency characteristic associated with a first low power mode supported by an audio device associated with the compute device, at least one of an amplifier or an equalizer of the audio device to be turned off in the first low power mode, the second audio latency characteristic associated with a second low power mode supported by digital signal processor circuitry of the compute device, the digital signal processor circuitry to enter low power operation in the second low power mode, the one or more audio latency requirements associated with an application on the compute device; cause the audio device to enter the first low power mode after a determination that the one or more audio latency requirements are met by the first audio latency characteristic; and cause the digital signal processor circuitry to enter the second low power mode after a determination that the one or more audio latency requirements are met by the second audio latency characteristic. 10. The at least one non-transitory computer readable medium of claim 9 , wherein the instructions are to cause one or more of the at least one processor circuit to: compare a third audio latency characteristic with the one or more audio latency requirements after the detection of the audio silence event, the third audio latency characteristic associated with a software layer of the compute device; and cause the software layer of the compute device to stop an audio stream associated with the audio silence event after a determination that the one or more audio latency requirements are met by the third audio latency characteristic. 11. The at least one non-transitory computer readable medium of claim 9 , wherein the audio silence event corresponds to a playback silence event, the audio device is an audio playback device, and the instructions are to cause one or more of the at least one processor circuit to: cause the digital signal processor circuitry to enter the second low power mode after the determination that the one or more audio latency requirements are met by the second audio latency characteristic and a determination that an operation condition is met, the operation condition to be met when a reference audio stream is not required by the application. 12. The at least one non-transitory computer readable medium of claim 11 , wherein the instructions are to cause one or more of the at least one processor circuit to: cause generation of fabricated audio data to include in the reference audio stream when the reference audio stream is required by the application. 13. The at least one non-transitory computer readable medium of claim 9 , wherein the audio silence event corresponds to a capture silence event, the audio device is an audio capture device, and the instructions are to cause one or more of the at least one process

Assignees

Inventors

Classifications

  • Management of the audio stream, e.g. setting of volume, audio stream path · CPC title

  • G06F3/162Primary

    Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US12190012B2 cover?
Example apparatus disclosed herein compare one or more audio latency characteristics with one or more audio latency requirements in response to detection of an audio silence event, the audio latency characteristic(s) associated with at least one of a hardware layer or a device layer of an audio stack of a compute device, the audio latency requirement(s) associated with an application. Disclosed…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F3/162. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 07 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).