Integrated circuit for security of a physically unclonable function and a device including the same

Patent metadata

Field	Value
Publication number	US-12189830-B2
Application number	US-202217847593-A
Country	US
Kind code	B2
Filing date	Jun 23, 2022
Priority date	Dec 31, 2018
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

An integrated circuit including: a plurality of physically unclonable function (PUF) cells each configured to generate a cell signal having a unique value; a selector configured to output a first signal obtained by not inverting a cell signal output by a PUF cell selected from the plurality of PUF cells and a second signal obtained by inverting the cell signal; and a key generator configured to generate a security key in response to the first signal or the second signal, wherein the selector includes a first conversion circuit configured to generate the first signal and a second conversion circuit having the same structure as the first conversion circuit and configured to generate the second signal.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
a plurality of physically unclonable function (PUF) cells each configured to generate a cell signal having a unique value;
a combination circuit configured to receive a plurality of signals from the plurality of PUF cells and output a combined signal, wherein the combination circuit is configured to perform a NAND operation;
a first XOR gate configured to receive a low level as a first input and receive the combined signal as a second input, wherein the first XOR gate is configured to output a first digital signal;
a second XOR gate configured to receive a high level as a first input and receive the combined signal as a second input, wherein the second XOR configured gate is to output a second digital signal;
wherein the second digital signal is an inverted signal of the first digital signal.

2. The IC of claim 1 , further comprising at least one flip-flop configured to receive the first digital signal and the second digital signal and generate a sampled first signal and a sampled second signal.

3. The IC of claim 2 , wherein the sampled first signal and the sampled second signal are inputted to a multiplexer.

4. The IC of claim 2 , further comprising a key generator configured to receive the sampled first signal.

5. The IC of claim 4 , wherein a security key is generated based on the sampled first signal.

6. The IC of claim 2 , wherein an XOR operation is performed on the sampled first signal and the sampled second signal.

7. The IC of claim 6 , wherein a fault insertion attack is detected based on a result of the XOR operation.

8. The IC of claim 1 , wherein each of the plurality of PUF cells comprises a first logic gate and a second logic gate, and
wherein the unique value of the cell signal output by a first PUF cell of the plurality of PUF cells is determined based on a difference between threshold levels of the first logic gate and the second logic gate.

9. An integrated circuit (IC), comprising:
a selection signal generator configured to generate a first selection signal and a second selection signal;
a plurality of physically unclonable function (PUF) blocks each configured to receive the first selection signal and each configured to generate a first output signal and a second output signal;
a multiplexer configured to receive the second selection signal from the selection signal generator and a plurality of first output signals from the plurality of PUF blocks, and further configured to output one of the plurality of first output signals;
a key generator configured to receive the one of the plurality of first output signals and generate a security key;
wherein each of the plurality of PUF blocks comprises at least one XOR gate and a plurality of PUF cells, wherein the output of the plurality of PUF cells is transmitted to the at least one XOR gate to generate an inverted signal and a non-inverted signal.

10. The IC of claim 9 , wherein the second output signal is an inverted signal of the first output signal.

11. The IC of claim 9 , wherein each of the plurality of PUF blocks comprises a plurality of PUF cells configured to generate cell signals having unique values, respectively.

12. The IC of claim 9 , wherein each of the PUF blocks is configured to generate an output signal based on a cell signal output by a PUF cell selected from the PUF cells in response to the first selection signal.

13. The IC of claim 9 , wherein the selection signal generator is configured to generate the first selection signal so that all of a plurality of PUF cells included in each of the plurality of PUF blocks are selected one-by-one.

14. The IC of claim 13 , wherein the selection signal generator is configured to generate the first selection signal so that the plurality of PUF cells are respectively selected at randomly delayed points in time.

15. The IC of claim 9 , wherein the plurality of PUF blocks are divided into two or more groups each of which includes a same number of PUF blocks, wherein the selection signal generator is configured to enable one of the two or more groups, and
wherein a plurality of PUF cells included in an enabled group are configured to generate output signals.

16. The IC of claim 9 , further comprising at least one flip-flop configured to receive the inverted signal and the non-inverted signal and generate the first output signal and the second output signal.

17. An integrated circuit (IC), comprising:
a physically unclonable function (PUF) block configured to output a first signal and a second signal, wherein the second signal is an inverted signal of the first signal;
a key generator configured to receive the first signal or the second signal and generate a security key;
an attack detector configured to receive the first signal and the second signal, and further configured to perform an XOR operation on the first signal and the second signal and further configured to output the result of the XOR operation to the key generator.

18. The IC of claim 17 , wherein a multiplexer is connected between the PUF block and the attack detector.

19. The IC of claim 17 , wherein a multiplexer is connected between the PUF block and the key generator.

20. The IC of claim 17 , wherein the PUF block comprises a plurality of PUF cells configured to generate cell signals having unique values.

21. The IC of claim 20 , wherein the PUF block comprises at least one XOR gate, wherein the at least one XOR gate receives an output of the plurality of PUF cells to generated the first signal and the second signal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Karpinskyy Bohdan
• Lee Yong-Ki
• Park Ji-Eun
• Ahn Kyoung-Moon
• Choi Yun-Hyeok

Classifications

• H10W42/405

  using active circuits · CPC title

• H04L9/0866 Primary

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• G06F21/72

  in cryptographic circuits · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• G06F21/566

  Dynamic detection, i.e. detection performed at run-time, e.g. emulation, suspicious activities · CPC title