Variable reference clock signal for data transmission between PHY layer and MAC layer

Patent metadata

Field	Value
Publication number	US-12189549-B2
Application number	US-202318126602-A
Country	US
Kind code	B2
Filing date	Mar 27, 2023
Priority date	Jul 30, 2021
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

First claim

What is claimed is:

1. An apparatus comprising:
a physical (PHY) layer and a media access control (MAC) layer, the PHY layer including:
a rate detection circuit configured to determine an adopted clock rate for data transmission between the PHY layer and the MAC layer, and in response, provide a rate detection signal indicative of the adopted clock rate;
a reference clock generator having an input coupled to the rate detection circuit and having a reference clock output, the reference clock generator configured to provide at the reference clock output a reference clock signal that is based on the rate detection signal; and
a PHY interface having a data input, a data output, and a clock input, in which the clock input is coupled to the reference clock output; and

the MAC layer including a MAC interface having a clock input coupled to the reference clock output, a data input coupled to the data output of the PHY interface, and a data output coupled to the data input of the PHY interface.

2. The apparatus of claim 1 , wherein the frequency of the reference clock signal is equal to the frequency of the adopted clock rate.

3. The apparatus of claim 1 , wherein the adopted clock rate is determined based on a rate negotiation protocol.

4. The apparatus of claim 1 , wherein the rate detection signal is varied responsive to the adopted clock rate.

5. The apparatus of claim 1 , wherein the frequency of the reference clock is varied responsive to the rate detection signal.

6. The apparatus of claim 1 , wherein the PHY interface is a reduced media independent interface (RMII).

7. The apparatus of claim 1 , wherein the MAC interface is a reduced media independent interface (RMII).

8. The apparatus of claim 1 , wherein the PHY and MAC interfaces are parallel bus interfaces.

9. The apparatus of claim 1 , wherein the PHY interface is configured to transfer data responsive to a rising edge of the reference clock signal.

10. The apparatus of claim 1 , wherein the PHY interface is configured to transfer data responsive to a falling edge of the reference clock signal.

11. The apparatus of claim 1 , wherein the PHY interface is configured to transfer data responsive to a rising edge and a falling edge of the reference clock signal.

12. A physical (PHY) layer comprising:
a rate detection circuit configured to determine an adopted clock rate having a frequency corresponding to a rate of data transmission between the PHY layer and a media access control (MAC) layer, and further configured to provide a rate detection signal indicative of the adopted clock rate at the output;
a reference clock generator having a reference clock output, the reference clock generator configured to provide, at the reference clock output and responsive to the rate detection signal, a reference clock signal having a frequency equal to the frequency of the adopted clock rate; and
a reduced media independent interface (RMII) having a reference clock input coupled to the reference clock output, the RMII configured to receive data from the MAC layer and transmit data to the MAC layer responsive to the reference clock signal.

13. The PHY layer of claim 12 , wherein the adopted clock rate is determined based on a rate negotiation protocol.

14. The PHY layer of claim 12 , wherein the rate detection signal is varied responsive to the adopted clock rate.

15. The PHY layer of claim 12 , wherein the frequency of the reference clock signal is varied responsive to the rate detection signal.

16. The PHY layer of claim 12 , wherein the RMII is configured to transmit and receive data responsive to a rising edge of the reference clock signal.

17. The PHY layer of claim 12 , wherein the RMII is configured to transmit and receive data responsive to a falling edge of the reference clock signal.

18. The PHY layer of claim 12 , wherein the RMII is configured to transmit and receive data responsive to a rising edge and a falling edge of the reference clock signal.

19. A method comprising:
determining an adopted clock rate corresponding to a rate of data transmission between a physical (PHY) layer and a media access control (MAC) layer;
generating, responsive to the adopted clock rate, a rate detection signal indicative of the adopted clock rate;
generating a reference clock signal responsive to the rate detection signal;
transmitting the reference clock signal to the PHY layer and to the MAC layer; and
transmitting data by the PHY layer to the MAC layer responsive to the reference clock signal and receiving data by the PHY layer from the MAC layer responsive to the reference clock signal.

20. The method of claim 19 , wherein the adopted clock rate is determined based on a rate negotiation protocol.

21. The method of claim 19 further comprising varying the rate of the reference clock signal responsive to the rate detection signal.

Assignees

• Texas Instruments Inc

Inventors

• Modi Geet Govind
• Seth Sumantra
• Mukherjee Subhashish

Classifications

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F13/20 Primary

  for access to input/output bus · CPC title