Processing system, related integrated circuit, device and method

Patent metadata

Field	Value
Publication number	US-12184448-B2
Application number	US-202318489590-A
Country	US
Kind code	B2
Filing date	Oct 18, 2023
Priority date	Aug 18, 2021
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

First claim

What is claimed is:

1. A processing system comprising:
a Serial Peripheral Interface (SPI) communication interface; and
a microprocessor communicatively connected to the SPI communication interface, wherein the microprocessor, when in a CAN FD Light data transmission mode, is configured to:
program a control register of the SPI communication interface in order to activate a master mode;
generate a transmission CAN FD Light frame;
store the transmission CAN FD Light frame to a memory; and
activate a first DMA channel so that the first DMA channel is able to sequentially transfer the transmission CAN FD Light frame from the memory to a transmission shift register of the SPI communication interface.

2. The processing system according to claim 1 , wherein the transmission shift register is configured to generate a transmission signal by sequentially providing its content in response to a first clock signal.

3. The processing system according to claim 2 , wherein SPI communication interface comprises a clock downscale circuit configured to:
receive a clock signal; and
generate a downscaled clock signal by downscaling the clock signal as a function of a clock scaling factor,
wherein the downscaled clock signal is the first clock signal.

4. The processing system according to claim 3 , wherein the control register is configured to store data identifying the clock scaling factor and data identifying a mode of operation, the mode of operation indicating the master mode or a slave mode.

5. The processing system according to claim 1 , further comprising activating, by the microprocessor, data transmission of the transmission CAN FD Light frame via a transmission terminal.

6. A method for operating a processing system comprising a Serial Peripheral Interface (SPI) communication interface and a microprocessor communicatively connected to the SPI communication interface, the method comprising:
programming, by the microprocessor, when in a CAN FD Light data transmission mode, a control register of the SPI communication interface in order to activate a master mode;
generating, by the microprocessor, a transmission CAN FD Light frame;
storing, by the microprocessor, the transmission CAN FD Light frame to a memory; and
activating, by the microprocessor, a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register of the SPI communication interface.

7. The method according to claim 6 , further comprising generating, by the transmission shift register, a transmission signal by sequentially providing its content in response to a first clock signal.

8. The method according to claim 7 , further comprising:
receiving, by the SPI communication interface, a clock signal; and
generating, by the SPI communication interface, a downscaled clock signal by downscaling the clock signal as a function of a clock scaling factor,
wherein the downscaled clock signal is the first clock signal.

9. The method according to claim 8 , wherein the control register is stores data identifying the clock scaling factor and data identifying a mode of operation, the mode of operation indicating the master mode or a slave mode.

10. The method according to claim 6 , further comprising activating, by the microprocessor, data transmission of the transmission CAN FD Light frame via a transmission terminal.

11. A processing system comprising:
a Serial Peripheral Interface (SPI) communication interface; and
a microprocessor communicatively connected to the SPI communication interface, wherein the microprocessor, when in a CAN FD Light data reception mode, is configured to:
program a control register of the SPI communication interface in order to activate a slave mode;
in response to receive a first control signal, enable a first hardware timer circuit and a second hardware timer circuit, wherein a second DMA channel is able to transfer packets of a given word size from a reception shift register to a memory thereby sequentially transferring a reception CAN FD Light frame from the reception shift register to the memory; and
in response to a second control signal, read the reception CAN FD Light frame from the memory.

12. The processing system according to claim 11 , wherein the reception shift register of the given word size is configured to sequentially add a logic level of a reception signal to a content of the reception shift register in response to a second clock signal.

13. The processing system according to claim 12 , further comprising an edge detector configured to assert the first control signal in response to detecting a falling edge in the reception signal.

14. The processing system according to claim 12 , wherein the SPI communication interface is configured to provide, in the slave mode, a clock signal received at a clock terminal as the second clock signal to the reception shift register.

15. The processing system according to claim 14 ,
wherein the first hardware timer circuit is configured to, when enabled, generate the clock signal at the clock terminal, and
wherein the second hardware timer circuit comprising a counter configured to, when enabled, increase a count value and assert the second control signal in response to determining that the count value reaches a given threshold value.

16. A method for operating a processing system comprising a Serial Peripheral Interface (SPI) communication interface and a microprocessor communicatively connected to the SPI communication interface, the method comprising:
programming, by the microprocessor, when in a CAN FD Light data reception mode, a control register of the SPI communication interface in order to activate a slave mode;
in response to receive a first control signal, enabling a first hardware timer circuit and a second hardware timer circuit, wherein a second DMA channel is able to transfer packets of a given word size from a reception shift register to a memory thereby sequentially transferring a reception CAN FD Light frame from the reception shift register to the memory; and
in response to a second control signal, reading the reception CAN FD Light frame from the memory.

17. The method according to claim 16 , further comprising sequentially adding, by the reception shift register of the given word size, a logic level of a reception signal to a content of the reception shift register in response to a second clock signal.

18. The method according to claim 17 , further comprising asserting, by an edge detector, the first control signal in response to detecting a falling edge in the reception signal.

19. The method according to claim 17 , further comprising providing, by the SPI communication interface, in the slave mode, a clock signal received at a clock terminal as the second clock signal to the reception shift register.

20. The method according to claim 19 , further comprising:
generating, by the first hardware timer circuit, when enabled, the clock signal at the clock terminal; and
increasing, by the second hardware timer circuit comprising a counter, when enabled, a count value and asserting the second control signal in response to determining that the count value reaches a given threshold value.

Assignees

• Stmicroelectronics Application Gmbh
• Stmicroelectronics Design & Application S R O

Inventors

• Dvorak Vaclav
• Rennig Fred

Classifications

• H04L2012/40215

  Controller Area Network CAN · CPC title

• H04L12/40169

  Flexible bus arrangements (arrangements for maintenance or administration involving management of faults; events, alarms H04L41/06; automatic restoration of network faults H04L41/0654) · CPC title

• G06F13/423

  with synchronous protocol · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/4068

  Electrical coupling · CPC title