Single-ended analog signal receiver apparatus

Patent metadata

Field	Value
Publication number	US-12184303-B2
Application number	US-202217982352-A
Country	US
Kind code	B2
Filing date	Nov 7, 2022
Priority date	Nov 12, 2021
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A single-ended analog signal receiver apparatus is provided, which can cope with an external ground current and an undefined impedance through an AC bootstrap input impedance, while considering electromagnetic compatibility, convert a received single-ended analog signal into a balanced output differential signal, and may provide at a post-stage circuit output an output signal with lower noise through common mode rejection.

First claim

What is claimed is:

1. A single-ended analog signal receiver apparatus for receiving a single-ended analog signal from an input signal terminal and outputting an output signal relative to a local ground terminal at an output terminal, the single-ended analog signal receiver apparatus comprising:
a buffer gain unit comprising:
a first buffer gain input terminal and a second buffer gain input terminal;
a first buffer gain output terminal and a second buffer gain output terminal,
a first bias resistor and a second bias resistor connected in series between the first buffer gain input terminal and the second buffer gain input terminal of the buffer gain unit;
a third bias resistor connected between a node between the first bias resistor and the second bias resistor and the local ground terminal;
a fourth bias resistor connected between the input signal terminal of the single-ended analog signal receiver apparatus and the first buffer gain input terminal of the buffer gain unit;
a fifth bias resistor connected between an input reference terminal of the single-ended analog signal receiver apparatus and the second buffer gain input terminal of the buffer gain unit;
a sixth bias resistor and a seventh bias resistor connected in series between the first buffer gain output terminal and the second buffer gain output terminal of the buffer gain unit;
a unity-gain amplifier unit comprising an input terminal and an output terminal, wherein the input terminal of the unity-gain amplifier unit is connected to a node between the sixth and seventh bias resistors;
a first capacitor connected between the output terminal of the unity-gain amplifier unit and a node between the first, second, and third bias resistors, the first capacitor being sized to have an impedance less than a resistance value of the third bias resistor at a frequency higher than a first predetermined frequency;
a second capacitor and a third capacitor connected in series between the input signal terminal and the input reference terminal of the unity-gain amplifier unit;
a fourth capacitor connected between a node between the second capacitor and the third capacitor and the local ground terminal; and
an eighth bias resistor connected between the output terminal of the unity-gain amplifier unit and a node between the second, third, and fourth capacitors, the fourth capacitor being sized to have an impedance less than a resistance value of the eighth bias resistor at a frequency lower than a second predetermined frequency,

a post-stage balance circuit unit with common mode rejection comprising:
a first post-stage input terminal and a second post-stage input terminal connected to the first buffer gain output terminal and the second buffer gain output terminal of the buffer gain unit, respectively; and
a post-stage output terminal connected to the output terminal of the single-ended analog signal receiver apparatus.

2. The single-ended analog signal receiver apparatus of claim 1 , wherein a resistance value ratio of the fourth bias resistor to the first bias resistor matches a resistance value ratio of the fifth bias resistor to the second bias resistor.

3. The single-ended analog signal receiver apparatus of claim 1 , wherein
the buffer gain unit further comprises a first operational amplifier and a second operational amplifier, and a first gain resistor, a second gain resistor, and a third gain resistor, wherein
a non-inverting input terminal of the first operational amplifier is connected to the first buffer gain input terminal of the buffer gain unit, a non-inverting input terminal of the second operational amplifier is connected to the second buffer gain input terminal of the buffer gain unit, the first gain resistor is connected between an inverting input terminal and an output terminal of the first operational amplifier, the second gain resistor is connected between the inverting input terminal of the first operational amplifier and an inverting input terminal of the second operational amplifier, and the third gain resistor is connected between the inverting input terminal and an output terminal of the second operational amplifier, wherein
the respective output terminals of the first operational amplifier and the second operational amplifier are connected to the first buffer gain output terminal and the second buffer gain output terminal of the buffer gain unit, respectively.

4. The single-ended analog signal receiver apparatus of claim 3 , wherein a resistance value of the third gain resistor matches a sum of resistance values of the first and second gain resistors.

5. The single-ended analog signal receiver apparatus of claim 3 , wherein a sum of resistance values of the first bias resistor and the fourth bias resistor is considerably greater than a sum of resistance values of the second bias resistor and the fifth bias resistor.

6. The single-ended analog signal receiver apparatus of claim 1 , where the input signal terminal and the input reference terminal comprise unmatched output impedances, respectively.

7. The single-ended analog signal receiver apparatus of claim 1 , wherein first predetermined frequency is about 1 Hz, and the second predetermined frequency is about 50,000 Hz.

8. The single-ended analog signal receiver apparatus of claim 1 ,
wherein the third capacitor is capable of being set to be considerably large to match the second and fifth bias resistors with small resistance values, and wherein the second capacitor is capable of being set to be small to match resistance values of the first and fourth bias resistors, so as to maintain a high common mode rejection ratio.

9. The single-ended analog signal receiver apparatus of claim 1 , wherein the unity-gain amplifier unit comprises a third operational amplifier, a non-inverting input terminal of the third operational amplifier is connected to the input terminal of the unity-gain amplifier unit, and an inverting input terminal of the third operational amplifier is connected to an output terminal of the third operational amplifier and connected to the output terminal of the unity-gain amplifier unit.

10. The single-ended analog signal receiver apparatus of claim 1 , wherein the post-stage balance circuit unit comprises an analog-to-digital converter (ADC) to reduce an output impedance of the buffer amplifying unit.

11. The single-ended analog signal receiver apparatus of claim 1 , further comprising:
a first balancing capacitor added between the connection of the fourth bias resistor and the first buffer gain input terminal of the buffer gain unit,
a second balancing capacitor added between the connection of the fifth bias resistor and the second buffer gain input terminal of the buffer gain unit,
a ninth bias resistor and a tenth bias resistor connected in series between the first buffer gain input terminal of the buffer gain unit and the second buffer gain input terminal of the buffer gain unit, and
a fifth capacitor connected between the output terminal of a unity-gain amplifier unit and a node between the ninth bias resistor and the tenth bias resistor,
wherein the single-ended analog signal receiver apparatus is further configured to provide a first single-rail power supply for the input signal terminal, a negative pole of the first single-rail power supply is connected to a local reference terminal, and a positive pole, after connected to a power supply bias resistor in series, is connected to the node between the ninth bias resistor and the tenth bias resistor.

12. The single-ended analog signal receiver apparatus of claim 1 , wherein the post-stage balance circuit unit comprises a fourth operational amplifier, a fourth gain resisto

Assignees

• Harman Int Ind

Inventors

• Greenslade Jason Anthony

Classifications

• H03M1/504

  using pulse width modulation · CPC title

• H03M1/205

  using resistor strings for redistribution of the original reference signals or signals derived therefrom · CPC title

• H03F3/45928

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45138

  Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers · CPC title

• H03F2200/261

  Amplifier which being suitable for instrumentation applications · CPC title