Active inductive simulator and impedance multiplier

Patent metadata

Field	Value
Publication number	US-12184256-B2
Application number	US-202418804325-A
Country	US
Kind code	B2
Filing date	Aug 14, 2024
Priority date	Sep 1, 2022
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A tunable grounded positive and negative active inductor simulator and impedance multiplier circuit and a method for implementing the tunable grounded positive and negative active inductor simulator and impedance multiplier circuit are described. The circuit includes one second generation voltage-mode conveyor circuit (VCII+), a voltage source configured to generate an output current, a first impedance, a second impedance and an operational transconductance amplifier OTA. The first impedance is connected between the voltage source and the positive VCII+ input terminal, Y. The second impedance is connected between the second output terminal and a ground terminal. The OTA is configured to have a transconductance gain. The circuit is configured to be tuned by a selection of values for the first and second impedances.

First claim

The invention claimed is:

1. A tunable inductor simulator and impedance multiplier circuit, comprising:
only one second-generation voltage-mode conveyor (VCII+), only one operational transconductance amplifier (OTA) and only two passive elements selected from the group consisting of a first impedance Z 1 and a second impedance Z 2 ;
wherein the one second generation voltage-mode conveyor circuit (VCII+) is configured with a positive VCII+ input terminal Y, a first output terminal Z, and a second output terminal X, wherein the VCII+ has a current gain β; and a voltage gain α;
a voltage source V s , configured to generate an output current at a frequency s;
wherein the first impedance Z 1 is connected between the voltage source and the positive VCII+ input terminal Y, wherein an internal circuit of the first impedance Z 1 , comprises a resistor R 1 , in parallel with a capacitor C 1 ;
wherein the second impedance Z 2 is connected between the second output terminal X, and a ground terminal, wherein an internal circuit of the second impedance Z 2 comprises a resistor R 2 in parallel with a capacitor C 2 ; and
wherein the operational transconductance amplifier OTA is configured to have a transconductance gain g m , wherein the OTA includes a positive OTA input terminal, a negative OTA input terminal, an OTA output terminal, and a current bias I B input terminal, wherein:
the positive OTA input terminal is connected to one of the first output terminal Z and the ground terminal;
the negative OTA input terminal is connected to one of the first output terminal Z and the ground terminal; and
the OTA output terminal is connected to the first impedance Z 1 , wherein the active inductor simulator and impedance multiplier circuit is configured to be tunable by a selection of a value for R 1 , a value for C 1 , a value for R 2 and a value for C 2 .

2. The inductor simulator and impedance multiplier circuit of claim 1 , wherein:
the OTA is configured to generate an output current I o ;
the positive VCII+ input terminal is configured to receive an input current I y , equal to the difference between I s and I 0 ;
the first output terminal Z is configured to generate a voltage V z ;
the second output terminal X is configured to generate a voltage V x across the second impedance Z 2 and a current i x through the second impedance Z 2 , wherein i x =±βI y and V z =αV x;
the output current I o is given by I o =I x Z 2 g m =−I y Z 2 g m ; and
a voltage at the positive VCII+ input terminal Y is given by V y , where V y =0.

3. The inductor simulator and impedance multiplier circuit of claim 2 , wherein:
the positive OTA input terminal is connected to the first output terminal Z;
the negative OTA input terminal is connected to the ground terminal, such that an input impedance Z in of the VCII+ is given by

Z

i
⁢
n

=

Z
1

1
+

Z
2

⁢

g
m

,

 where Z 2 g m is ≤1.

4. The inductor simulator and impedance multiplier circuit of claim 3 , wherein:
a tunable positive active inductor simulator is configured by setting Z 1 =R 1 , C 1 =0, R 2 =0 and Z 2 =1/sC 2 , such that the input impedance is given by

Z

i
⁢
n

=

s
⁢

C
2

⁢

R
1

20
×

I
B

=

s
⁢
L

 where

L
=

C
2

⁢

R
1

20
×

I
B

;

 and
a value of the inductor L is tuned by the selection of the value of C 2 and the value of R 1 .

5. The inductor simulator and impedance multiplier circuit of claim 3 , wherein:
a tunable positive capacitance multiplier is configured by setting Z 1 =1/sC 1 , R 1 =0, Z 2 =R 2 , and C 2 =0, such that the input impedance is given by

Z

i
⁢
n

=

1

s
⁢

C
1

(

1
+

2
⁢
0
×

R
2

⁢

I
B

)

,

 in which the capacitance C 1 is multiplied by (1+20×R 2 I B ); and
an amount of multiplication of C 1 is tuned by the selection of the value of R 2 .

6. The inductor simulator and impedance multiplier circuit of claim 3 , wherein:
a tunable positive resistance multiplier is configured by setting Z 1 =R 1 , C 1 =0, Z 2 =R 2 , C 2 =0, such that the input impedance is given by

Z

i
⁢
n

=

Assignees

• Univ King Fahd Pet & Minerals

Inventors

• Al-Absi Muneer A
• Al-Khulaifi Abdulaziz

Classifications

• H03H11/405

  Positive impedance converters (H03H11/42 takes precedence; used in frequency selective networks H03H11/0416) · CPC title

• H03H11/44

  Negative impedance converters (H03H11/42 takes precedence) · CPC title

• H03H11/486 Primary

  Simulating inductances using transconductance amplifiers · CPC title