Switching power supply current sensing, zero-crossing detection and overvoltage protection

Patent metadata

Field	Value
Publication number	US-12184198-B2
Application number	US-202217895272-A
Country	US
Kind code	B2
Filing date	Aug 25, 2022
Priority date	Aug 26, 2021
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A control circuit for a switching power supply, can include: a sampling circuit configured to obtain an inductor current and a drain-source voltage of a main power transistor in a power stage circuit, in order to generate a sampling signal; where the control circuit generates an inductor current sampling signal according to the sampling signal during an on-period of the main power transistor; and where during an off-period of the main power transistor, the control circuit generates a zero-crossing signal of the inductor current and an overvoltage signal of an output voltage of the switching power supply according to the sampling signal.

First claim

What is claimed is:

1. A control circuit for a switching power supply, the control circuit comprising:
a) a sampling circuit configured to obtain an inductor current and a drain-source voltage of a main power transistor in a power stage circuit, in order to generate a sampling signal;
b) wherein the control circuit generates an inductor current sampling signal according to the sampling signal during an on-period of the main power transistor,
c) wherein during an off-period of the main power transistor, the control circuit generates a zero-crossing signal of the inductor current and an overvoltage signal of an output voltage of the switching power supply according to the sampling signal; and
d) wherein the sampling circuit comprises a current sampling circuit configured to obtain the inductor current and generate the inductor current sampling signal, a differential circuit comprising a first capacitor and a third resistor, and being configured to generate a differential signal by differentiating the drain-source voltage when the main power transistor is turned off, and a voltage divider circuit configured to divide the drain-source voltage to obtain a voltage divider signal when the main power transistor is turned off.

2. The control circuit of claim 1 , wherein the control circuit comprises a control chip, the sampling signal is transmitted to a detection circuit inside the control chip through a multiplexer detection pin, and the detection circuit receives the sampling signal and generates the inductor current sampling signal, the zero-crossing signal, and the overvoltage signal.

3. The control circuit of claim 2 , wherein a first terminal of the differential circuit is connected to a drain of the main power transistor, a second terminal of the differential circuit is connected to a source of the main power transistor, a third terminal of the differential circuit is coupled to the multiplexer detection pin.

4. The control circuit of claim 3 , wherein a first terminal of the voltage divider circuit is connected to the drain of the main power transistor, a second terminal of the voltage divider circuit is connected to the source of the main power transistor through the differential circuit, and a third terminal of the voltage divider circuit is connected to the multiplexer detection pin, and the voltage divider signal is generated at the third terminal of the voltage divider circuit.

5. The control circuit of claim 3 , wherein a first terminal of the voltage divider circuit is connected to the drain of the main power transistor, a second terminal of the voltage divider circuit is connected to the source of the main power transistor, and a third terminal of the voltage divider circuit is connected to the multiplexer detection pin through the differential circuit, and the voltage divider signal is generated at the third terminal of the voltage divider circuit.

6. The control circuit of claim 5 , wherein the sampling circuit comprises a current limiting resistor, and the differential circuit is connected to the multiplexer detection pin through the current limiting resistor.

7. The control circuit of claim 3 , wherein a first terminal of the first capacitor is connected to the drain of the main power transistor, and a second terminal of the first capacitor is connected to one terminal of the third resistor, the other terminal of the third resistor is connected to the source of the main power transistor, the second terminal of the first capacitor is also coupled to the multiplexer detection pin.

8. The control circuit of claim 2 , wherein the detection circuit comprises a first detection circuit for receiving the sampling signal at the multiplexer detection pin, and during the on-period of the main power transistor, when the sampling signal reaches an overcurrent threshold representing inductor current overcurrent information, an overcurrent signal is activated.

9. The control circuit of claim 2 , wherein the detection circuit is configured to receive the sampling signal at the multiplexer detection pin, and the sampling signal is configured as the inductor current sampling signal during the on-period of the main power transistor.

10. The control circuit of claim 2 , wherein the detection circuit comprises a second detection circuit for receiving the sampling signal at the multiplexer detection pin, and during the off-period of the main power transistor, when the sampling signal reaches an overvoltage threshold representing output voltage overvoltage information, the overvoltage signal is activated.

11. The control circuit of claim 2 , wherein the detection circuit comprises a third detection circuit for receiving the sampling signal at the multiplexer detection pin, and during the off-period of the main power transistor, when the sampling signal reaches a zero-crossing threshold representing a zero-crossing information of the inductor current, the zero-crossing signal is activated.

12. The control circuit of claim 1 , wherein in one switching cycle, a first interval of the sampling signal is configured as the inductor current sampling signal representing the inductor current during the on-period of the main power transistor.

13. The control circuit of claim 1 , wherein in one switching cycle, a second interval of the sampling signal is configured as a voltage divided signal representing the drain-source voltage of the main power transistor.

14. The control circuit of claim 1 , wherein in one switching cycle, a third interval of the sampling signal is configured as a differential signal representing a change rate of the drain-source voltage of the main power transistor.

15. The control circuit of claim 1 , wherein the control circuit is configured to obtain an overcurrent signal of the inductor current according to the sampling signal during the on-period of the main power transistor.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Chen Chaojun

Classifications

• H02M3/33523

  with galvanic isolation between input and output of both the power stage and the feedback loop · CPC title

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title

• H02M1/4258

  using a single converter stage both for correction of AC input power factor and generation of a regulated and galvanically isolated DC output voltage (H02M1/4241 takes precedence) · CPC title

• H02M1/4225

  using a non-isolated boost converter · CPC title