Comparator-based switched-capacitor circuit and current source thereof

Patent metadata

Field	Value
Publication number	US-12184170-B2
Application number	US-202218086720-A
Country	US
Kind code	B2
Filing date	Dec 22, 2022
Priority date	Mar 22, 2022
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A comparator-based switched-capacitor circuit has a first output terminal and a second output terminal, and includes a switch-capacitor network, a first current source, and a second current source. Each of the first current source and the second current source includes a first transistor, a second transistor, a capacitor, and a buffer circuit. The first transistor has a first source, a first drain, and a first gate. The first drain is coupled to the first output terminal, the first source is coupled to a reference voltage, and the first gate is coupled to the switch-capacitor network. The second transistor has a second source, a second drain, and a second gate. The second source is coupled to the first output terminal. The capacitor is coupled between the second gate and the second source. The buffer circuit is coupled between the second source and the second drain.

First claim

What is claimed is:

1. A comparator-based switched-capacitor (SC) circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal and comprising:
a comparator;
a first switch;
a second switch;
a third switch;
a fourth switch;
a fifth switch;
a sixth switch;
a seventh switch;
an eighth switch;
a ninth switch;
a tenth switch;
a first capacitor having a first end and a second end, the first end being coupled to the first input terminal through the first switch and coupled to the first output terminal through the fourth switch, the second end being coupled to the comparator and coupled to a first reference voltage through the third switch;
a second capacitor having a third end and a fourth end, the third end being coupled to the first input terminal through the second switch and coupled to the first reference voltage through the fifth switch, the fourth end being coupled to the comparator and coupled to the first reference voltage through the third switch;
a third capacitor having a fifth end and a sixth end, the fifth end being coupled to the second input terminal through the sixth switch and coupled to the second output terminal through the ninth switch, the sixth end being coupled to the comparator and coupled to the first reference voltage through the eighth switch;
a fourth capacitor having a seventh end and an eighth end, the seventh end being coupled to the second input terminal through the seventh switch and coupled to the first reference voltage through the tenth switch, the eighth end being coupled to the comparator and coupled to the first reference voltage through the eighth switch;
a first transistor having a first source, a first drain, and a first gate, the first drain being coupled to the first output terminal, the first source being coupled to a second reference voltage, and the first gate being coupled to the comparator;
a second transistor having a second source, a second drain, and a second gate, the second source being coupled to the first output terminal;
a fifth capacitor coupled between the second gate and the second source;
a first buffer circuit coupled between the first output terminal and the second drain;
a third transistor having a third source, a third drain, and a third gate, the third drain being coupled to the second output terminal, the third source being coupled to a third reference voltage, and the third gate being coupled to the comparator;
a fourth transistor having a fourth source, a fourth drain, and a fourth gate, the fourth source being coupled to the second output terminal;
a sixth capacitor coupled between the fourth gate and the fourth source; and
a second buffer circuit coupled between the second output terminal and the fourth drain.

2. The comparator-based SC circuit of claim 1 , wherein the first buffer circuit is configured to amplify a signal at the first output terminal by N times, and the second buffer circuit is configured to amplify a signal at the second output terminal by N times, N being greater than one.

3. The comparator-based SC circuit of claim 2 , wherein N is substantially equal to two.

4. A current source having a first input terminal and a first output terminal and comprising:
a first transistor having a first gate, a first source, and a first drain, wherein the first gate is coupled to the first input terminal, the first source is coupled to a reference voltage, and the first drain is coupled to the first output terminal;
a second transistor having a second gate, a second source, and a second drain, wherein the second source is coupled to the first output terminal;
a capacitor coupled between the second gate and the second source and used to bias the second transistor; and
a buffer circuit having a second input terminal and a second output terminal, wherein the second input terminal is coupled to the second source, and the second output terminal is coupled to the second drain.

5. The current source of claim 4 , wherein the second input terminal is further coupled to the first output terminal, and the buffer circuit is configured to amplify a signal at the first output terminal by N times, N being greater than one.

6. The current source of claim 5 , wherein N is substantially equal to two.

7. A comparator-based switched-capacitor (SC) circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal and comprising:
a comparator;
a first switch;
a second switch;
a third switch;
a fourth switch;
a fifth switch;
a sixth switch;
a seventh switch;
an eighth switch;
a ninth switch;
a tenth switch;
a first current source coupled to the comparator and the first output terminal;
a second current source coupled to the comparator and the second output terminal;
a first capacitor having a first end and a second end, the first end being coupled to the first input terminal through the first switch and coupled to the first output terminal through the fourth switch, the second end being coupled to the comparator and coupled to a first reference voltage through the third switch;
a second capacitor having a third end and a fourth end, the third end being coupled to the first input terminal through the second switch and coupled to the first reference voltage through the fifth switch, the fourth end being coupled to the comparator and coupled to the first reference voltage through the third switch;
a third capacitor having a fifth end and a sixth end, the fifth end being coupled to the second input terminal through the sixth switch and coupled to the second output terminal through the ninth switch, the sixth end being coupled to the comparator and coupled to the first reference voltage through the eighth switch; and
a fourth capacitor having a seventh end and an eighth end, the seventh end being coupled to the second input terminal through the seventh switch and coupled to the first reference voltage through the tenth switch, the eighth end being coupled to the comparator and coupled to the first reference voltage through the eighth switch;
wherein the first current source comprises:
a first transistor having a first source, a first drain, and a first gate, the first drain being coupled to the first output terminal, the first source being coupled to a second reference voltage, and the first gate being coupled to the comparator;
a second transistor having a second source, a second drain, and a second gate, the second source being coupled to the first output terminal;
a fifth capacitor coupled between the second gate and the second source; and
a buffer circuit having a third input terminal and a third output terminal, the third input terminal being coupled to the second source, and the third output terminal being coupled to the second drain.

8. The comparator-based SC circuit of claim 7 , wherein the third input terminal is further coupled to the first output terminal, and the buffer circuit is configured to amplify a signal at the first output terminal by N times, N being greater than one.

9. The comparator-based SC circuit of claim 8 , wherein N is substantially equal to two.

10. The comparator-based SC circuit of claim 8 , wherein the buffer circuit is a first buffer circuit, and the second current source comprises:
a third transistor having a third source, a third drain, and a third gate, the third drain being coupled to the second output terminal, the third source being coupled to a third reference voltage, and the third gate being coupled to the comparator;
a fourth transistor having a fourth source, a fourth drain, and a fourth gate, the fourth source being coupled to the second output terminal;
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Assignees

• Realtek Semiconductor Corp

Inventors

• Huang Shih-Hsiung
• Hong Wei-Cian

Classifications

• H03K5/24 Primary

  the characteristic being amplitude · CPC title

• H03M1/361

  having a separate comparator and reference value for each quantisation level, i.e. full flash converter type · CPC title

• H03M1/167

  all stages comprising simultaneous converters (H03M1/165 takes precedence) · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title