Display panel

Patent metadata

Field	Value
Publication number	US-12183286-B2
Application number	US-202318482453-A
Country	US
Kind code	B2
Filing date	Oct 6, 2023
Priority date	Dec 30, 2022
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

Provided is a display panel including a light-emitting element, and a pixel circuit electrically connected to the light-emitting element, and including a driving unit electrically connected to the light-emitting element, the driving unit including a first transistor including a first bottom electrode for receiving a first voltage, and a first semiconductor pattern including an oxide semiconductor above the first bottom electrode, and at least one diode including a second bottom electrode for receiving a second voltage at a same layer as the first bottom electrode, and a second semiconductor pattern above the second bottom electrode, at a same layer as the first semiconductor pattern, including an oxide semiconductor, and integrated with the first semiconductor pattern.

First claim

What is claimed is:

1. A display panel comprising:
a light-emitting element; and
a pixel circuit electrically connected to the light-emitting element, and comprising a driving unit electrically connected to the light-emitting element, the driving unit comprising:
a first transistor comprising a first bottom electrode for receiving a first voltage, and a first semiconductor pattern comprising an oxide semiconductor above the first bottom electrode; and
at least one diode comprising a second bottom electrode for receiving a second voltage at a same layer as the first bottom electrode, and a second semiconductor pattern above the second bottom electrode, at a same layer as the first semiconductor pattern, comprising an oxide semiconductor, and integrated with the first semiconductor pattern.

2. The display panel of claim 1 , wherein the first bottom electrode is electrically connected to the second semiconductor pattern.

3. The display panel of claim 1 , wherein the first bottom electrode is spaced from the second bottom electrode.

4. The display panel of claim 1 , wherein the at least one diode comprises:
a first diode comprising a second-first bottom electrode for receiving a second-first voltage at the same layer as the first bottom electrode, and a second-first semiconductor pattern comprising an oxide semiconductor above the second-first bottom electrode and at the same layer as the first semiconductor pattern; and
an n th diode comprising a second-n th bottom electrode for receiving a second-n th voltage at the same layer as the first bottom electrode, and a second-n th semiconductor pattern comprising an oxide semiconductor above the second-n th bottom electrode and at the same layer as the first semiconductor pattern.

5. The display panel of claim 4 , wherein the second-first bottom electrode is integrated with the second-n th bottom electrode.

6. The display panel of claim 4 , wherein the second-first voltage is equal to the second-n th voltage.

7. The display panel of claim 1 , wherein the first bottom electrode is integrated with the second bottom electrode.

8. The display panel of claim 1 , wherein the first transistor comprises a first insulating pattern above the first semiconductor pattern, and a first gate electrode above the first insulating pattern, and
wherein the at least one diode comprises a second insulating pattern above the second semiconductor pattern, and a second gate electrode above the second insulating pattern.

9. The display panel of claim 8 , wherein the first semiconductor pattern comprises a first source region, a first drain region, and a first channel region,
wherein the first insulating pattern overlaps the first channel region, but does not overlap the first source region and the first drain region,
wherein the second semiconductor pattern comprises a second source region, a second drain region, and a second channel region, and
wherein the second insulating pattern overlaps the second channel region, but does not overlap the second source region and the second drain region.

10. The display panel of claim 9 , wherein an extension length of the first channel region in a first direction is less than an extension length of the second channel region in the first direction.

11. The display panel of claim 9 , wherein the first source region is electrically connected to the second drain region and to the second gate electrode.

12. The display panel of claim 9 , wherein the pixel circuit further comprises a first connection electrode connected to the first source region and to the second gate electrode.

13. The display panel of claim 1 , wherein the second bottom electrode and the second semiconductor pattern are electrically connected to the light-emitting element.

14. The display panel of claim 1 , wherein the first voltage is equal to the second voltage.

15. The display panel of claim 1 , wherein the pixel circuit further comprises:
at least one cover insulating layer configured to cover the first transistor and the at least one diode; and
a connection electrode above the cover insulating layer, passing through at least a portion of the cover insulating layer, and connected to the driving unit.

16. The display panel of claim 1 , wherein the light-emitting element comprises:
a first electrode electrically connected to the driving unit;
a second electrode above the first electrode; and
a light-emitting layer between the first electrode and the second electrode.

17. The display panel of claim 1 , wherein the pixel circuit further comprises a second transistor comprising a third semiconductor pattern comprising an oxide semiconductor at the same layer as the first semiconductor pattern and spaced from the first semiconductor pattern.

18. A display panel comprising:
a light-emitting element; and
a pixel circuit electrically connected to the light-emitting element, and comprising a first circuit unit electrically connected to the light-emitting element and comprising:
a first transistor comprising a first bottom electrode for receiving a first voltage, and a first semiconductor pattern comprising an oxide semiconductor above the first bottom electrode; and
at least one diode comprising a second bottom electrode for receiving a second voltage, electrically connected to the light-emitting element, and at a same layer as the first bottom electrode, and a second semiconductor pattern comprising an oxide semiconductor, electrically connected to the light-emitting element, and located above the second bottom electrode and at a same layer as the first semiconductor pattern.

19. The display panel of claim 18 , wherein the first semiconductor pattern comprises a first source region, a first drain region, and a first channel region,
wherein the second semiconductor pattern comprises a second source region, a second drain region electrically connected to the first source region, and a second channel region.

20. A display panel comprising:
a light-emitting element; and
a pixel circuit electrically connected to the light-emitting element, and comprising a first circuit unit electrically connected to the light-emitting element, the first circuit unit comprising:
a first transistor comprising a first bottom electrode for receiving a first voltage, and a first semiconductor pattern comprising an oxide semiconductor above the first bottom electrode; and
at least one diode comprising a second bottom electrode for receiving a second voltage at a same layer as the first bottom electrode, and a second semiconductor pattern comprising an oxide semiconductor above the second bottom electrode at a same layer as the first semiconductor pattern,

wherein the first bottom electrode is electrically connected to the second bottom electrode or to the second semiconductor pattern.

Assignees

• Samsung Display Co Ltd

Inventors

• Son Kyoung Seok
• Kim Myeongho
• Kim Youngoo
• Kim Jaybum
• Lee Seunghun

Classifications

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10K59/123 Primary

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title

• H10K59/1213 Primary

  the pixel elements being TFTs · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title