Demultiplex type display driving circuit
US-2018047353-A1 · Feb 15, 2018 · US
US12183240B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12183240-B2 |
| Application number | US-202318106418-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 6, 2023 |
| Priority date | Aug 2, 2018 |
| Publication date | Dec 31, 2024 |
| Grant date | Dec 31, 2024 |
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A display panel includes a first pixel group including sub-pixels coupled to a first scan line and located in first through N-th sub-pixel columns, where N is an even number greater than or equal to 2, a second pixel group including sub-pixels coupled to the first scan line and located in (N+1)-th through 2N-th sub-pixel columns, a third pixel group including sub-pixels coupled to a second scan line adjacent to the first scan line and located in the first through N-th sub-pixel columns, and a fourth pixel group including sub-pixels coupled to the second scan line and located in the (N+1)-th through 2N-th sub-pixel columns. The first pixel group and the second pixel group are driven during a first scan on time in which the first scan line is driven. Consecutive N−1 sub-pixels among the sub-pixels of the third pixel group and one sub-pixel among the sub-pixels of the fourth pixel group are driven during a first portion of a second scan on time in which the second scan line is driven, and consecutive N−1 sub-pixels among the sub-pixels of the fourth pixel group and one sub-pixel among the sub-pixels of the third pixel group are driven during a second portion of the second scan on time.
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What is claimed is: 1. A display panel comprising: a plurality of sub-pixels disposed on a substrate, the plurality of sub-pixels being disposed in a matrix configuration having a plurality of columns and a plurality of rows; first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth data lines sequentially disposed along a row direction, and a plurality of source channel lines, wherein each of the plurality of source channel lines is connected to at least three data lines, wherein the second, third, sixth and seventh data lines are coupled to first demux switches receiving a same first demux control signal, and wherein the first data line is connected to one of the plurality of source channel lines with at least two other data lines, wherein the plurality of sub-pixels includes: a first R sub-pixel, a first G sub-pixel, a first B sub-pixel, a first G′ sub-pixel, a second R sub-pixel, a second G sub-pixel, a second B sub-pixel and a second G′ sub-pixel sequentially disposed along the row direction in a first row of the plurality of rows, and wherein the first R sub-pixel, the first G sub-pixel, the first B sub-pixel, the first G′ sub-pixel, the second R sub-pixel, the second G sub-pixel, the second B sub-pixel and the second G′ sub-pixel are coupled to the second, third, sixth, seventh, tenth, eleventh, fourteenth and fifteenth data lines, respectively. 2. The display panel of claim 1 , wherein the first and sixteenth data lines are coupled to second demux switches receiving a same second demux control signal. 3. The display panel of claim 1 , wherein the first, fourth and fifth data lines are coupled to second demux switches receiving a same second demux control signal. 4. The display panel of claim 1 , wherein the eighth, ninth, twelfth and thirteenth data lines are coupled to second demux switches receiving a same second demux control signal. 5. The display panel of claim 1 , wherein the tenth, eleventh, fourteenth and fifteenth data lines are coupled to second demux switches receiving a same second demux control signal, wherein the first, fourth, fifth and sixteenth data lines are coupled to third demux switches receiving a same third demux control signal, and wherein the eighth, ninth, twelfth and thirteenth data lines are coupled to fourth demux switches receiving a same fourth demux control signal. 6. The display panel of claim 1 , wherein the first, third, fifth, seventh, ninth, eleventh, thirteenth and fifteenth data lines are disposed at left sides of first through eighth columns of the plurality of columns, and wherein the second, fourth, sixth, eighth, tenth, twelfth, fourteenth and sixteenth data lines are disposed at right sides of the first through eighth columns. 7. The display panel of claim 1 , wherein the plurality of sub-pixels includes: a third B sub-pixel, a third G′ sub-pixel, a third R sub-pixel, a third G sub-pixel, a fourth B sub-pixel, a fourth G′ sub-pixel, a fourth R sub-pixel and a fourth G sub-pixel sequentially disposed along the row direction in a second row of the plurality of rows. 8. The display panel of claim 7 , wherein the third B sub-pixel, the third G′ sub-pixel, the third R sub-pixel, the third G sub-pixel, the fourth B sub-pixel, the fourth G′ sub-pixel, the fourth R sub-pixel and the fourth G sub-pixel are coupled to the first, fourth, fifth, eighth, ninth, twelfth, thirteenth and sixteenth data lines, respectively. 9. The display panel of claim 7 , wherein a first scan on time for the first row includes a first sub-scan on time and a second sub-scan on time, the first R sub-pixel, the first G sub-pixel, the first B sub-pixel and the first G′ sub-pixel are driven during the first sub-scan on time, and the second R sub-pixel, the second G sub-pixel, the second B sub-pixel and the second G′ sub-pixel are driven during the second sub-scan on time, and wherein a second scan on time for the second row includes a third sub-scan on time and a fourth sub-scan on time, the third B sub-pixel, the third G′ sub-pixel, the third R sub-pixel and the fourth G sub-pixel are driven during the third sub-scan on time, and the third G sub-pixel, the fourth B sub-pixel, the fourth G′ sub-pixel and the fourth R sub-pixel are driven during the fourth sub-scan on time.
Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title
Details of driving circuits arranged to drive both scan and data electrodes · CPC title
Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title
Layout of electrodes and connections · CPC title
Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling · CPC title
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