Executing a composite scalar-vector VLIW instruction having a repeat field

Patent metadata

Field	Value
Publication number	US-12182576-B2
Application number	US-201916731214-A
Country	US
Kind code	B2
Filing date	Dec 31, 2019
Priority date	Mar 31, 2016
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the composite VLIW instruction to perform the operation.

First claim

What is claimed is:

1. A processor core comprising:
a memory which stores multiple composite very large instruction word (VLIW) instructions;
an instruction circuit which obtains the multiple composite VLIW instructions from the memory and decodes the multiple composite VLIW instructions to determine an operation to perform; and
a composite VLIW instruction execution unit which executes the multiple composite VLIW instructions to perform the operation, wherein the composite VLIW instruction execution unit comprises a detector circuit which determines whether a respective REPEAT (REP) field in each of the multiple composite VLIW instructions is REP=1 or REP>1,
wherein the multiple composite VLIW instructions comprise a first composite VLIW instruction and a second composite VLIW instruction,
wherein in response to the detector circuit determining that the REP field in the first composite VLIW instruction is REP=1, the composite VLIW instruction execution unit executes each atom in the first composite VLIW instruction at a single iteration, and
wherein in response to the detector circuit determining that the REP field in the second composite VLIW instruction comprises a value of REP>1, the composite VLIW instruction execution unit executes each vector atom of the second composite VLIW instruction for a number of iterations greater than one that is equal to the value of the REP field and executes each scalar atom of the second composite VLIW instruction for a single iteration.

2. The processor core of claim 1 , wherein the first composite VLIW instruction includes a scalar atom, and
wherein the composite VLIW instruction execution unit includes a default setting which sets an iteration at which the scalar atom of the first composite VLIW instruction is to be executed.

3. The processor core of claim 2 , wherein the scalar atom of the first composite VLIW instruction indicates an iteration at which the scalar atom of the first composite VLIW instruction is to be executed.

4. The processor core of claim 3 , wherein the first composite VLIW instruction further comprises a vector atom and a control atom,
wherein each scalar atom indicates an iteration at which the respective scalar atom is to be executed instead of the iteration set by the default setting.

5. The processor core of claim 1 , wherein the composite VLIW instruction execution unit further comprises a composite VLIW instruction execution subunit that executes each scalar atom of the second composite VLIW instruction at a respective single iteration.

6. The processor core of claim 5 , wherein the composite VLIW instruction execution subunit executes branch and control atoms of the second composite VLIW instruction at a single iteration.

7. The processor core of claim 6 , wherein the single iteration at which the composite VLIW instruction execution subunit executes the branch and control atoms of the second composite VLIW instruction comprises a last iteration.

8. The processor core of claim 6 , wherein the branch and control atoms of the second composite VLIW instruction comprise a field indicating the iteration at which the composite VLIW instruction execution subunit executes the branch and control atoms.

9. The processor core of claim 6 , wherein the composite VLIW instruction execution unit comprises an iteration setting circuit which, based on a user input:
adjusts a first default setting that sets an iteration at which the branch and control atoms of the second composite VLIW instruction are executed; and
adjusts a second default setting that sets an iteration at which each scalar atom of the second composite VLIW instruction is to be executed.

10. The processor core of claim 5 , wherein the composite VLIW instruction execution subunit executes a first scalar atom of multiple scalar atoms of the second composite VLIW instruction at a first iteration that precedes at least one other iteration.

11. The processor core of claim 10 , wherein the first scalar atom of the second composite VLIW instruction comprises a field indicating the iteration at which the composite VLIW instruction execution subunit executes the first scalar atom, and
wherein the first scalar atom and a vector atom are combined in the second composite VLIW instruction.

12. A method of executing multiple composite very large instruction word (VLIW) instructions, the method comprising:
storing in a memory, the multiple composite VLIW instructions, wherein the multiple composite VLIW instructions comprise a first composite VLIW instruction and a second composite VLIW instruction;
obtaining the multiple composite VLIW instructions from the memory and decoding the multiple composite VLIW instructions to determine an operation to perform; and
using a composite VLIW instruction execution unit, executing the multiple composite VLIW instructions to perform the operation, wherein the composite VLIW instruction execution unit comprises a detector circuit which determines whether a respective REPEAT (REP) field in each of the multiple composite VLIW instructions is REP=1 or REP>1, and
wherein in response to the detector circuit determining that the REP field in the first composite VLIW instruction is REP=1, the composite VLIW instruction execution unit executes each atom in the first composite VLIW instruction at a single iteration, and
wherein in response to the detector circuit determining that the REP field in the second composite VLIW instruction comprises a value of REP>1, the composite VLIW instruction execution unit executes each vector atom of the second composite VLIW instruction for a number of iterations greater than one that is equal to the value of the REP field and executes each scalar atom of the second composite VLIW instruction for a single iteration.

13. The method of claim 12 , wherein the first composite VLIW instruction includes a scalar atom, and
wherein the composite VLIW instruction execution unit includes a default setting which sets an iteration at which the scalar atom of the first composite VLIW instruction is to be executed.

14. The method of claim 13 , wherein the scalar atom of the first composite VLIW instruction indicates an iteration at which the scalar atom of the first composite VLIW instruction is to be executed.

15. The method of claim 12 , further comprising:
executing branch and control atoms of the second composite VLIW instruction at a single iteration,
wherein each scalar atom indicates an iteration at which the respective scalar atom is to be executed instead of the iteration set by a default setting in the composite VLIW instruction execution unit.

16. A programmable non-transitory storage medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus to perform a method of executing multiple composite very large instruction word (VLIW) instructions, the method comprising:
storing in a memory, the multiple composite VLIW instructions, wherein the multiple composite VLIW instructions comprise a first composite VLIW instruction and a second composite VLIW instruction;
obtaining the multiple composite VLIW instructions from the memory and decoding the multiple composite VLIW instructions to determine an operation to perform; and
using a composite VLIW instruction execution unit, executing the multiple composite VLIW instructions to perform the operation, wherein the composite VLIW instruction execution unit comprises a detector circuit which determines whether a respective REPEAT (REP) field in each of the multiple composite VLIW instructions is REP=1 or REP>1,
wherein in

Assignees

• IBM

Inventors

• Fleischer Bruce M
• Fox Thomas Winters
• Jacob Arpith C
• Jacobson Hans Mikael
• Nair Ravi
• O'Brien Kevin John Patrick
• Prener Daniel Arthur

Classifications

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/30065

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title

• G06F9/3853 Primary

  of compound instructions · CPC title

• G06F9/3822

  Parallel decoding, e.g. parallel decode units · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title