Hardware support for software event collection

Patent metadata

Field	Value
Publication number	US-12182003-B1
Application number	US-202217647539-A
Country	US
Kind code	B1
Filing date	Jan 10, 2022
Priority date	Aug 31, 2021
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

An apparatus includes a processor circuit that includes a memory circuit, one or more processor cores, and a debug circuit. The debug circuit may be configured, in response to activation of a trace mode to record information indicative of instructions executing on the one or more processor cores, to write a trace data stream to the memory circuit that includes trace data collected on the instructions executing on the one or more processor cores. In response to a particular instruction within one of the processor cores specifying a write of a data value to an architecturally visible trace register, the debug circuit may be further configured to output the data value to the trace data stream as part of executing the particular instruction.

First claim

What is claimed is:

1. An apparatus, comprising:
a processor circuit comprising:
a memory circuit;
one or more processor cores; and
a debug circuit that includes an architecturally visible trace register that is accessible by at least a particular one of the one or more processor cores, the debug circuit configured, in response to activation of a trace mode to;
observe and record trace data indicative of instructions executing on the one or more processor cores; and
write a trace data stream to the memory circuit that includes the recorded trace data;

wherein the particular processor core is configured to:
in response to execution of a particular instruction, write a data value indicated by the particular instruction to the architecturally visible trace register; and

wherein the debug circuit is further configured to:
annotate, as part of executing the particular instruction, the trace data stream with an insertion of the data value into the trace data stream.

2. The apparatus of claim 1 , wherein the debug circuit is further configured to:
based on the write to the trace register, initiate a timer;
attempt to locate an idle cycle in the trace data stream to insert the data value from the trace register; and
in response to a determination that the timer has reached a threshold value and the idle cycle has not occurred:
stall the instructions executing on the one or more processor cores; and
insert the data value from the trace register into the trace data stream.

3. The apparatus of claim 1 , wherein the debug circuit is further configured to output a current data value of the trace register in response to a determination that a particular period of time has elapsed since a previous output of the data value.

4. The apparatus of claim 3 , wherein the debug circuit is further configured to output respective current data values of particular core registers with the current data value of the trace register.

5. The apparatus of claim 4 , wherein the debug circuit is further configured to cease output of the trace data recorded from the instructions executing on the one or more processor cores while maintaining periodic output of current data values of the trace register and the particular core registers.

6. The apparatus of claim 1 , wherein the debug circuit is further configured to:
output trace data corresponding to call instructions and return instructions executed by the one or more processor cores; and
omit trace data corresponding to other instructions executed by the one or more processor cores.

7. The apparatus of claim 1 , wherein the particular processor core is further configured to write the data value to the trace register in a single cycle of a system clock signal.

8. A method, comprising:
in response to an activation of a trace mode to record information associated with a program executing on a processor core, generating, by a debug circuit, a trace data stream that includes trace data collected on the executing program;
executing, by the processor core, a particular instruction in the program that specifies a write of a data value to an architecturally visible trace register in the debug circuit;
waiting, by the processor core, for an idle cycle in the trace data stream to insert the data value; and
annotating, by the debug circuit as part of executing the particular instruction, the idle cycle in the trace data stream with the data value from the trace register.

9. The method of claim 8 , wherein annotating the trace data stream includes:
in response to determining that a threshold amount of time has elapsed without the idle cycle, generating, by the debug circuit, the idle cycle by stalling the program executing on the processor core.

10. The method of claim 8 , further comprising, in response to an activation of a register trace mode to record values of a particular set of core registers, annotating, by the debug circuit, the trace data stream with respective data values from the particular set of core registers in response to determining that a particular period of time has elapsed since a previous annotating.

11. The method of claim 10 , further comprising determining, by the debug circuit, the particular set of core registers using a value of a programmable selector register.

12. The method of claim 10 , further comprising:
determining, by the debug circuit, the particular period of time using a programmable timer; and
in response to determining that the particular period of time is less than a threshold amount of time, deactivating the register trace mode.

13. The method of claim 10 , wherein annotating the trace data stream includes:
stalling, by the debug circuit in response to the particular period of time elapsing, the program executing on the processor core; and
inserting, by the debug circuit, the respective data values from the particular set of core registers into the trace data stream during the stalling.

14. The method of claim 10 , wherein the trace register is included in the particular set of core registers.

15. A system, comprising:
a memory circuit;
a processor circuit including one or more processor cores and a debug circuit with a trace register, wherein the processor circuit is configured, to:
in response to activation of a mode to record trace data indicative of instruction execution by the one or more processor cores, use the debug circuit to stream the trace data to the memory circuit;
based on a determination that a particular period of time has elapsed since a previous output of a current data value stored in the trace register, use the debug circuit to insert the current data value of the trace register into the trace data stream;
in response to execution of a particular instruction by a given one of the one or more processor cores, use the given processor core to write a data value indicated by the particular instruction to the trace register without altering an architectural state of the one or more processor cores, wherein the trace register is directly addressable by the given processor core; and
in response to a determination that the data value has been written to the trace register, use the debug circuit to insert the data value from the trace register into the trace data stream.

16. The system of claim 15 , wherein the processor circuit is further configured to use the debug circuit to:
attempt to locate an idle cycle in the trace data stream to insert the data value from the trace register; and
in response to a determination that a threshold amount of time has elapsed without an idle cycle:
stall instructions executing on the one or more processor cores; and
insert the data value from the trace register into the trace data stream.

17. The system of claim 15 , wherein the processor circuit is further configured, in response to activation of a different mode, to use the debug circuit to:
output, into the trace data stream, information indicative of execution of call instructions and return instructions by the one or more processor cores; and
ignore information indicative of other instructions executed by the one or more processor cores.

18. The system of claim 17 , wherein the processor circuit is further configured, in response to the activation of the different mode, to cause the processor cores to retire a maximum of one branch instruction per clock cycle.

19. The system of claim 17 , wherein the processor circuit is further configured to activate the different mode in response to an indication of improper operation.

Assignees

• Apple Inc

Inventors

• Patwardhan Jaidev P
• Knoth Matthias
• Srikantaiah Shekhar S
• Malhotra Prakhar
• Widmann Matthew C
• Solomonov Dmitriy B
• Pistol Constantin

Classifications

• G06F11/3476

  Data logging (G06F11/14, G06F11/2205 take precedence) · CPC title

• G06F11/3656

  using a specific debug interface · CPC title

• G06F11/3636 Primary

  by tracing the execution of the program · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/0757

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title