Automatic overclocking controller based on circuit delay measurement

Patent metadata

Field	Value
Publication number	US-12181911-B2
Application number	US-202318224579-A
Country	US
Kind code	B2
Filing date	Jul 21, 2023
Priority date	Jan 6, 2023
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

An automatic overclocking controller based on circuit delay measurement is provided, including a central processing unit (CPU), a clock generator, and a timing delay monitor (TDM) controller. Compared with the prior art, the present disclosure has following innovative points: A two-dimension-multi-frame fusion (2D-MFF) technology is used to process a sampling result, to eliminate sampling noise, and an automatic overclocking controller running on a heterogeneous field programmable gate array (FPGA) can automatically search for a highest frequency at which an accelerator can operate safely.

First claim

What is claimed is:

1. An automatic overclocking controller based on a circuit delay measurement, comprising a central processing unit (CPU), a clock generator, and a timing delay monitor (TDM) controller, wherein
a phase of a shadow clock (SCLK) output by the clock generator is adjusted from 0° to 360°, the TDM controller controls a circuit delay detector to sample the clock generator N times in a same phase before moving to a next phase, until the clock generator is sampled in all phases, and a final sampling value of each phase of the all phases is an average value of sampling values obtained from N times of sampling in a current phase;
the TDM controller is further configured to perform a horizontal multi-frame fusion on final sampling values of the all phases to obtain transition points θ 1 and θ 2 ;
when the horizontal multi-frame fusion is performed, the final sampling value of each phase is defined as one frame of data; therefore, an n th frame of data obtained after the horizontal multi-frame fusion is an average value of an

(

n
-

M
-
1

2

)

t
⁢
h

frame of data to an

(

n
+

M
-
1

2

)

t
⁢
h

frame of data, wherein M represents a coefficient of the horizontal multi-frame fusion;
the transition point θ 1 is a point wherein a sampling value changes from 0 to 1 after the horizontal multi-frame fusion, and the transition point θ 2 is a point wherein a sampling value changes from 1 to 0 after the horizontal multi-frame fusion; and
the CPU is configured to obtain the transition points θ 1 and θ 2 from the TDM controller to calculate a circuit delay t d , and determine a frequency f next of an accelerator for a next operating cycle based on the circuit delay t d .

2. The automatic overclocking controller based on the circuit delay measurement according to claim 1 , wherein if the average value of the sampling values obtained from the N times of sampling in the current phase is not greater than 0.5, a final sampling value of the current phase is 0, and if the average value of the sampling values obtained from the N times of sampling in the current phase is greater than 0.5, a final sampling value of the current phase is 1.

3. The automatic overclocking controller based on the circuit delay measurement according to claim 1 , wherein the TDM controller comprises a sampler and a transition point finder, wherein the sampler controls the circuit delay detector to obtain the final sampling values of the all phases and perform the horizontal multi-frame fusion, and the transition point finder searches for the transition points θ 1 and θ 2 .

4. The automatic overclocking controller based on the circuit delay measurement according to claim 3 , wherein the sampler shares a plurality of circuit delay detectors, and the CPU calculates a plurality of circuit delays t d for a plurality of paths by using the plurality of circuit delay detectors, and selects a longest circuit delay t d from the plurality of circuit delays t d to determine the frequency f next of the accelerator for the next operating cycle.

5. The automatic overclocking controller based on the circuit delay measurement according to claim 1 , wherein the CPU calculates the circuit delay t d according to a following formula:

t
d

=

θ

3
⁢
6
⁢
0

·
T

wherein

θ
=

θ
1

+

θ
2

+

180
⁢
°

2

,

and T represents a clock cycle.

Assignees

• Univ Shanghai Technology

Inventors

• Jiang Weixiong
• Ha Yajun

Classifications

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• H04B17/364

  Delay profiles · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title