Display substrate and display panel for reducing crosstalk

Patent metadata

Field	Value
Publication number	US-12181761-B2
Application number	US-202117773412-A
Country	US
Kind code	B2
Filing date	Jul 7, 2021
Priority date	Aug 27, 2020
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

An Embodiment of the present disclosure provide a display substrate, including a base substrate, and a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a plurality of common electrodes and a plurality of pixel electrodes on the base substrate. The second scanning lines are parallel to the data lines, and the second scanning lines, the common electrodes and the pixel electrodes are in different layers. The common electrodes are located on a side of the second scanning lines and the data lines away from the base substrate, and on a side of the pixel electrodes proximal to the base substrate. An orthographic projection of one of the data line and the second scanning line on the base substrate is located in a spacer region between adjacent pixel electrodes.

First claim

What is claimed is:

1. A display substrate, comprising a base substrate, and a first scanning line, a second scanning line, a data line, a common electrode and a plurality of pixel electrodes on the base substrate; wherein
the second scanning line is parallel to the data line, and the second scanning line, the common electrode and the plurality of pixel electrodes are in different layers; and the common electrode is located on a side of the second scanning line and the data line away from the base substrate, and on a side of the plurality of pixel electrodes proximal to the base substrate; and
an orthographic projection of one of the data line and the second scanning line on the base substrate is located in a spacer region between adjacent pixel electrodes of the plurality of pixel electrodes, and an orthographic projection of the other of the data line and the second scanning line on the base substrate overlaps orthographic projections of a part of pixel electrodes of the plurality of pixel electrodes on the base substrate.

2. The display substrate according to claim 1 , wherein
the orthographic projection of the data line on the base substrate is located on a center line of the orthographic projections of the part of pixel electrodes on the base substrate, and the orthographic projection of the second scanning line on the base substrate is located in the spacer region between the adjacent pixel electrodes.

3. The display substrate according to claim 1 , wherein
the second scanning line is disposed in the same layer as the data line; the first scanning line is disposed on a side of the second scanning line proximal to the base substrate, a first insulation layer is provided between the second scanning line and the first scanning line, and the second scanning line is connected to the first scanning lines through a via formed in the first insulation layer to provide an input signal for the first scanning line;
the common electrode and the plurality of pixel electrodes are disposed on a side of the second scanning line away from the base substrate, and the common electrode and the plurality of pixel electrodes are sequentially arranged away from the base substrate and correspond to each other; a second insulation layer is provided between the common electrode and the second scanning line; and a third insulation layer is provided between the common electrode and the plurality of pixel electrodes.

4. The display substrate according to claim 3 , comprising a plurality of first scanning lines wherein
the plurality of pixel electrodes are arranged in an array, the plurality of first scanning lines extend in a row direction of the array, and a spacer region between any two adjacent rows of pixel electrodes is provided with one of the plurality of first scanning lines.

5. The display substrate according to claim 1 , wherein one of the data line and the second scanning line with the orthographic projection thereof on the base substrate overlapping the orthographic projections of the part of pixel electrodes on the base substrate has a width greater than a width of the other of the data line and the second scanning line with the orthographic projection thereof on the base substrate located in the spacer region between the adjacent pixel electrodes.

6. The display substrate according to claim 1 , wherein the second scanning line has the same thickness as the data line; and
the second insulation layer comprises a first sub-layer with a thickness greater than a thickness of the data line, and a thickness ratio of the first sub-layer to the data line ranges from 3: 1 to 9:1.

7. The display substrate according to claim 6 , wherein the second insulation layer further comprises a second sub-layer, the second sub-layer and the first sub-layer being stacked sequentially away from the base substrate; and
the first sub-layer has a thickness greater than a thickness of the second sub-layer, and a thickness ratio of the second sub-layer to the first sub-layer ranges from 1:25 to 1:10.

8. The display substrate according to claim 4 , comprising a plurality of data lines and a plurality of second scanning lines wherein
the plurality of data lines and the plurality of second scanning lines extend in a column direction,
a number of the plurality of second scanning lines is smaller than a number of the plurality of data lines;
the display substrate further comprises a plurality of common electrode lines on the base substrate, wherein the plurality of common electrode lines and the plurality of second scanning lines are disposed in a same layer and parallel to each other;
the orthographic projections of the plurality of data lines on the base substrate overlap the orthographic projections of the part of pixel electrodes on the base substrate, orthographic projections of the plurality of common electrode lines on the base substrate are respectively located in spacer regions between adjacent pixel electrodes of the plurality of pixel electrodes, and no second scanning line is provided in the spacer regions between the adjacent pixel electrodes.

9. The display substrate according to claim 8 , wherein the plurality of second scanning lines and the plurality of common electrode lines are alternately arranged along an arrangement direction of the plurality data lines, and any two adjacent second scanning line and the common electrode line has a same distance therebetween.

10. The display substrate according to claim 8 , further comprising a plurality of switch transistors each comprising a gate electrode, the first insulation layer, an active layer, a source electrode and a drain electrode; wherein the gate electrode is disposed in the same layer as the first scanning lines, the first insulation layer and the active layer are sequentially stacked on a side of the gate electrode away from the base substrate, the source electrode and the drain electrode are disposed in the same layer as the data lines and on a side of the active layer away from the base substrate, and the source electrode and the drain electrode are disposed at two opposite sides of the active layer respectively and connected to the active layer;
the drain electrodes of the switch transistors are respectively connected to corresponding pixel electrodes; the source electrodes of the switch transistors are respectively connected to corresponding data lines; and the gate electrodes of the switch transistors corresponding to rows of pixel electrodes are respectively connected to corresponding first scanning lines; and
among columns of pixel electrodes, the source electrodes of the switch transistors corresponding to odd-numbered columns of pixel electrodes are correspondingly connected to one of the data lines, the source electrodes of the switch transistors corresponding to even-numbered columns of pixel electrodes are correspondingly connected to another one of the data lines, with the one data line being adjacent to the another data line.

11. The display substrate according to claim 10 , wherein the switch transistors connected to a same data line are respectively disposed at two sides or a same side of the data line, and disposed proximal to the data line.

12. The display substrate according to claim 8 , wherein a number of the plurality of second scanning lines is n times a number of the plurality of first scanning lines, where n is an integer, and n=1, 2, 3 . . .

13. The display substrate according to claim 12 , wherein adjacent second scanning lines has a same distance therebetween, and points at connection positons where the plurality of second scanning lines are respectively connected to the plurality of first scanning

Assignees

• Hefei Boe Display Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zhang Yuntian
• Zhou Maoxiu
• Yang Haipeng
• Dai Ke
• Li Mengmeng
• Liao Yanping
• Guo Lei

Classifications

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/134309 Primary

  characterised by their geometrical arrangement · CPC title

• G09G2310/0232

  Special driving of display border areas · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G3/3614

  Control of polarity reversal in general · CPC title