Systems and methods for asymmetric image splitter clock generation

Patent metadata

Field	Value
Publication number	US-12177604-B2
Application number	US-202318093802-A
Country	US
Kind code	B2
Filing date	Jan 5, 2023
Priority date	Jun 13, 2018
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.

First claim

What is claimed is:

1. A device supporting image multi-streaming comprising:
a first interface that receives a super-frame image signal comprising a first image stream and a second image stream;
an asymmetric image splitter engine coupled to receive the super-frame image signal, the asymmetric image splitter engine splits the super-frame image signal into the first image stream and the second image stream; and
a fractional clock divider that receives a super-frame clock, the fractional clock divider generates a first clock to drive the first image stream by dividing a frequency of the super-frame clock by a first amount and generates a second clock to drive the second image stream by dividing the frequency of the super-frame clock by a second amount, the super-frame clock, the first clock and the second clock having different frequencies, the fractional clock divider comprises a sigma-delta modulator that uses an accumulator to allow sigma-delta modulation, the fractional clock divider further comprises:
a comparator block that compares an output from the accumulator to a number of pixels in the super-frame and generates a comparator output; and
a clock gate that receives the comparator output to gate the super-frame clock and outputs the first clock to drive the first image stream and the second clock to drive the second image stream.

2. The device of claim 1 , wherein the first amount is related to a ratio of the number of pixels in a frame in the first image stream and the number of pixels in the super-frame, the second amount is related to a ratio of a number of pixels in a frame in the second image stream and a number of pixels in the super-frame when the fractional clock divider operates in an open loop operation mode.

3. The device of claim 1 , wherein the fractional clock divider further comprises a feedback control loop, the feedback control loop comprising:
a counter outputting a counter value that increases for every super-frame clock active pixel and decreases for every split display pixel;
a first multiplier generating an error signal that is a difference between the counter value and a threshold; and
a second multiplier multiplying the error signal by a feedback gain to obtain a proportional error for adjusting a number of pixels in a split display's frame.

4. The device of claim 3 , wherein the counter is a first-in-first-out (FIFO) counter.

5. The device of claim 3 , wherein the threshold and the feedback gain are programmable.

6. A method for asymmetric image splitter clock generation comprising:
receiving a super-frame image signal comprising a first image stream and a second image stream;
splitting, using an asymmetric image splitter engine, the super-frame image signal into the first image stream and the second image stream; and
generating, using a fractional clock divider, a first clock to drive the first image stream and a second clock to drive the second image stream from a super-frame clock of the super-frame image signal, the super-frame clock, the first clock and the second clock having different frequencies, the first clock is obtained by dividing a frequency of the super-frame clock by a first amount and the second clock is obtained by dividing the frequency of the super-frame clock by a second amount, the fractional clock divider comprises a sigma-delta modulator that uses an accumulator to allow sigma-delta modulation, wherein generating the first clock and the second clock comprises:
comparing, using a comparator block in the fractional clock divider, an output from the accumulator to a number of pixels in the super-frame to generate a comparator output; and
gating, using a clock gate in the fractional clock divider based on the comparator output, the super-frame clock to output the first clock to drive the first image stream and the second clock to drive the second image stream.

7. The method of claim 6 , wherein the fractional clock divider comprises a feedback control loop, the feedback control loop comprising:
a counter outputting a counter value that increases for every super-frame clock active pixel and decreases for every split display pixel;
a first multiplier generating an error signal that is a difference between the counter value and a threshold; and
a second multiplier multiplying the error signal by a feedback gain to obtain a proportional error for adjusting a number of pixels in a split display's frame.

8. The method of claim 7 , wherein the counter is a first-in-first-out (FIFO) counter.

9. The method of claim 7 , wherein the threshold and the feedback gain are programmable.

10. The method of claim 6 , wherein in the super-frame image signal, the first image stream has a height higher than the second image stream.

11. A system for image multi-streaming comprising:
a first circuit that outputs a super-frame image signal comprising a first image stream and a second image stream;
an asymmetric image splitter engine that splits the super-frame image signal into the first image stream and the second image stream;
a fractional clock divider that generates a first clock to drive the first image stream and a second clock to drive the second image stream from a super-frame clock of the super-frame image signal, the super-frame clock, the first clock and the second clock having different frequencies;
a first deserializer that receives the first image stream for displaying using the first clock; and
a second deserializer that receives the second image stream for displaying using the second clock.

12. The system of claim 11 , wherein the super-frame image signal comprises image streams from Light Detection and Ranging (LIDAR) devices, radar, or other sensors.

13. The system of claim 11 , wherein the fractional clock divider comprises a sigma-delta modulator that uses an accumulator to allow sigma-delta modulation.

14. The system of claim 13 , wherein the fractional clock divider further comprises:
a comparator block that compares an output from the accumulator to a number of pixels in the super-frame and generates a comparator output; and
a clock gate that receives the comparator output to gate the super-frame clock and outputs the first clock to drive the first image stream and the second clock to drive the second image stream.

15. The system of claim 14 , wherein the fractional clock divider further comprises a feedback control loop, the feedback control loop comprising:
a counter outputting a counter value that increases for every super-frame clock active pixel and decreases for every split display pixel;
a first multiplier generating an error signal that is a difference between the counter value and a threshold; and
a second multiplier multiplying the error signal by a feedback gain to obtain a proportional error for adjusting a number of pixels in a split display's frame.

16. The system of claim 14 , wherein the threshold and the feedback gain are programmable.

Assignees

• Maxim Integrated Products

Inventors

• Balcioglu Yalcin

Classifications

• H04N2201/04768

  Controlling the frequency of the signals · CPC title

• H04N21/41422 Primary

  located in transportation means, e.g. personal vehicle (arrangements specially adapted for transportation systems in broadcast systems H04H20/62) · CPC title

• H04N21/2365

  Multiplexing of several video streams · CPC title

• H04N21/234

  Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs · CPC title

• H04N7/108

  the cable being constituted by a pair of wires · CPC title